bool Filler::delayHasHazard(const MachineInstr &Candidate, RegDefsUses &RegDU,
InspectMemInstr &IM) const {
bool HasHazard = (Candidate.isImplicitDef() || Candidate.isKill());
HasHazard |= IM.hasHazard(Candidate);
HasHazard |= RegDU.update(Candidate, 0, Candidate.getNumOperands());
return HasHazard;
}
bool Filler::delayHasHazard(const MachineInstr &Candidate, RegDefsUses &RegDU,
InspectMemInstr &IM) const {
assert(!Candidate.isKill() &&
"KILL instructions should have been eliminated at this point.");
bool HasHazard = Candidate.isImplicitDef();
HasHazard |= IM.hasHazard(Candidate);
HasHazard |= RegDU.update(Candidate, 0, Candidate.getNumOperands());
return HasHazard;
}
bool Filler::examinePred(MachineBasicBlock &Pred, const MachineBasicBlock &Succ,
RegDefsUses &RegDU, bool &HasMultipleSuccs,
BB2BrMap &BrMap) const {
std::pair<MipsInstrInfo::BranchType, MachineInstr *> P =
getBranch(Pred, Succ);
// Return if either getBranch wasn't able to analyze the branches or there
// were no branches with unoccupied slots.
if (P.first == MipsInstrInfo::BT_None)
return false;
if ((P.first != MipsInstrInfo::BT_Uncond) &&
(P.first != MipsInstrInfo::BT_NoBranch)) {
HasMultipleSuccs = true;
RegDU.addLiveOut(Pred, Succ);
}
BrMap[&Pred] = P.second;
return true;
}
bool Filler::delayHasHazard(const MachineInstr &Candidate, bool &SawLoad,
bool &SawStore, RegDefsUses &RegDU) const {
bool HasHazard = (Candidate.isImplicitDef() || Candidate.isKill());
// Loads or stores cannot be moved past a store to the delay slot
// and stores cannot be moved past a load.
if (Candidate.mayStore() || Candidate.hasOrderedMemoryRef()) {
HasHazard |= SawStore | SawLoad;
SawStore = true;
} else if (Candidate.mayLoad()) {
HasHazard |= SawStore;
SawLoad = true;
}
assert((!Candidate.isCall() && !Candidate.isReturn()) &&
"Cannot put calls or returns in delay slot.");
HasHazard |= RegDU.update(Candidate, 0, Candidate.getNumOperands());
return HasHazard;
}
