bool
RegisterContextDarwin_x86_64::WriteRegister (const RegisterInfo *reg_info,
const RegisterValue &value)
{
const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
int set = RegisterContextDarwin_x86_64::GetSetForNativeRegNum (reg);
if (set == -1)
return false;
if (ReadRegisterSet(set, false) != 0)
return false;
switch (reg)
{
case gpr_rax:
case gpr_rbx:
case gpr_rcx:
case gpr_rdx:
case gpr_rdi:
case gpr_rsi:
case gpr_rbp:
case gpr_rsp:
case gpr_r8:
case gpr_r9:
case gpr_r10:
case gpr_r11:
case gpr_r12:
case gpr_r13:
case gpr_r14:
case gpr_r15:
case gpr_rip:
case gpr_rflags:
case gpr_cs:
case gpr_fs:
case gpr_gs:
(&gpr.rax)[reg - gpr_rax] = value.GetAsUInt64();
break;
case fpu_fcw:
fpu.fcw = value.GetAsUInt16();
break;
case fpu_fsw:
fpu.fsw = value.GetAsUInt16();
break;
case fpu_ftw:
fpu.ftw = value.GetAsUInt8();
break;
case fpu_fop:
fpu.fop = value.GetAsUInt16();
break;
case fpu_ip:
fpu.ip = value.GetAsUInt32();
break;
case fpu_cs:
fpu.cs = value.GetAsUInt16();
break;
case fpu_dp:
fpu.dp = value.GetAsUInt32();
break;
case fpu_ds:
fpu.ds = value.GetAsUInt16();
break;
case fpu_mxcsr:
fpu.mxcsr = value.GetAsUInt32();
break;
case fpu_mxcsrmask:
fpu.mxcsrmask = value.GetAsUInt32();
break;
case fpu_stmm0:
case fpu_stmm1:
case fpu_stmm2:
case fpu_stmm3:
case fpu_stmm4:
case fpu_stmm5:
case fpu_stmm6:
case fpu_stmm7:
::memcpy (fpu.stmm[reg - fpu_stmm0].bytes, value.GetBytes(), value.GetByteSize());
break;
case fpu_xmm0:
case fpu_xmm1:
case fpu_xmm2:
case fpu_xmm3:
case fpu_xmm4:
case fpu_xmm5:
case fpu_xmm6:
case fpu_xmm7:
case fpu_xmm8:
case fpu_xmm9:
case fpu_xmm10:
case fpu_xmm11:
case fpu_xmm12:
case fpu_xmm13:
case fpu_xmm14:
case fpu_xmm15:
::memcpy (fpu.xmm[reg - fpu_xmm0].bytes, value.GetBytes(), value.GetByteSize());
return false;
case exc_trapno:
exc.trapno = value.GetAsUInt32();
break;
case exc_err:
exc.err = value.GetAsUInt32();
break;
case exc_faultvaddr:
exc.faultvaddr = value.GetAsUInt64();
break;
default:
return false;
}
return WriteRegisterSet(set) == 0;
}
bool
RegisterContextPOSIXProcessMonitor_x86_64::WriteRegister(const RegisterInfo *reg_info, const RegisterValue &value)
{
const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
if (IsGPR(reg))
return WriteRegister(reg, value);
if (IsFPR(reg, GetFPRType()))
{
switch (reg)
{
default:
if (reg_info->encoding != eEncodingVector)
return false;
if (reg >= fpu_stmm0 && reg <= fpu_stmm7)
::memcpy (m_fpr.xstate.fxsave.stmm[reg - fpu_stmm0].bytes, value.GetBytes(), value.GetByteSize());
if (reg >= fpu_xmm0 && reg <= fpu_xmm15)
::memcpy (m_fpr.xstate.fxsave.xmm[reg - fpu_xmm0].bytes, value.GetBytes(), value.GetByteSize());
if (reg >= fpu_ymm0 && reg <= fpu_ymm15) {
if (GetFPRType() != eXSAVE)
return false; // the target processor does not support AVX
// Store ymm register content, and split into the register halves in xmm.bytes and ymmh.bytes
::memcpy (m_ymm_set.ymm[reg - fpu_ymm0].bytes, value.GetBytes(), value.GetByteSize());
if (false == CopyYMMtoXSTATE(reg, GetByteOrder()))
return false;
}
break;
case fpu_dp:
m_fpr.xstate.fxsave.dp = value.GetAsUInt64();
break;
case fpu_fcw:
m_fpr.xstate.fxsave.fcw = value.GetAsUInt16();
break;
case fpu_fsw:
m_fpr.xstate.fxsave.fsw = value.GetAsUInt16();
break;
case fpu_ip:
m_fpr.xstate.fxsave.ip = value.GetAsUInt64();
break;
case fpu_fop:
m_fpr.xstate.fxsave.fop = value.GetAsUInt16();
break;
case fpu_ftw:
m_fpr.xstate.fxsave.ftw = value.GetAsUInt16();
break;
case fpu_mxcsr:
m_fpr.xstate.fxsave.mxcsr = value.GetAsUInt32();
break;
case fpu_mxcsrmask:
m_fpr.xstate.fxsave.mxcsrmask = value.GetAsUInt32();
break;
}
if (WriteFPR())
{
if (IsAVX(reg))
return CopyYMMtoXSTATE(reg, GetByteOrder());
return true;
}
}
return false;
}
bool
RegisterContextDarwin_i386::WriteRegister (const RegisterInfo *reg_info,
const RegisterValue &value)
{
const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
int set = GetSetForNativeRegNum (reg);
if (set == -1)
return false;
if (ReadRegisterSet(set, false) != 0)
return false;
switch (reg)
{
case gpr_eax:
case gpr_ebx:
case gpr_ecx:
case gpr_edx:
case gpr_edi:
case gpr_esi:
case gpr_ebp:
case gpr_esp:
case gpr_ss:
case gpr_eflags:
case gpr_eip:
case gpr_cs:
case gpr_ds:
case gpr_es:
case gpr_fs:
case gpr_gs:
(&gpr.eax)[reg - gpr_eax] = value.GetAsUInt32();
break;
case fpu_fcw:
fpu.fcw = value.GetAsUInt16();
break;
case fpu_fsw:
fpu.fsw = value.GetAsUInt16();
break;
case fpu_ftw:
fpu.ftw = value.GetAsUInt8();
break;
case fpu_fop:
fpu.fop = value.GetAsUInt16();
break;
case fpu_ip:
fpu.ip = value.GetAsUInt32();
break;
case fpu_cs:
fpu.cs = value.GetAsUInt16();
break;
case fpu_dp:
fpu.dp = value.GetAsUInt32();
break;
case fpu_ds:
fpu.ds = value.GetAsUInt16();
break;
case fpu_mxcsr:
fpu.mxcsr = value.GetAsUInt32();
break;
case fpu_mxcsrmask:
fpu.mxcsrmask = value.GetAsUInt32();
break;
case fpu_stmm0:
case fpu_stmm1:
case fpu_stmm2:
case fpu_stmm3:
case fpu_stmm4:
case fpu_stmm5:
case fpu_stmm6:
case fpu_stmm7:
// These values don't fit into scalar types, RegisterContext::ReadRegisterBytes()
// must be used for these registers
::memcpy (fpu.stmm[reg - fpu_stmm0].bytes, value.GetBytes(), value.GetByteSize());
return false;
case fpu_xmm0:
case fpu_xmm1:
case fpu_xmm2:
case fpu_xmm3:
case fpu_xmm4:
case fpu_xmm5:
case fpu_xmm6:
case fpu_xmm7:
// These values don't fit into scalar types, RegisterContext::ReadRegisterBytes()
// must be used for these registers
::memcpy (fpu.xmm[reg - fpu_xmm0].bytes, value.GetBytes(), value.GetByteSize());
return false;
case exc_trapno:
exc.trapno = value.GetAsUInt32();
break;
case exc_err:
exc.err = value.GetAsUInt32();
break;
case exc_faultvaddr:
exc.faultvaddr = value.GetAsUInt32();
break;
default:
return false;
}
return WriteRegisterSet(set) == 0;
}