string Operator::buildVHDLRegisters() {
ostringstream o,l;
if (isSequential()){
if(getClkName().compare("") == 0) {
std::cerr << "-- Can't find clock port for sequential component" << std::endl;
return "";
}
std::string clk = getClkName();
o << "-- clkname = " << clk << endl;
o << tab << "process("<< clk <<") begin\n"
<< tab << tab << "if "<< clk << "'event and "<< clk <<"= '1' then\n";
for(unsigned int i=0; i<signalList_.size(); i++) {
Signal *s = signalList_[i];
if(s->getLifeSpan() >0) {
for(int j=1; j <= s->getLifeSpan(); j++)
l << tab <<tab << tab << s->delayedName(j) << " <= " << s->delayedName(j-1) <<";" << endl;
}
}
// when there are not registers then we don't need that process stmnt
if (l.str().compare("") == 0) return l.str();
o << l.str();
o << tab << tab << "end if;\n";
o << tab << "end process;\n";
}
return o.str();
}
string Operator::use(string name) throw(std::string) {
ostringstream e;
e << "ERROR in use(), "; // just in case
if(isSequential()) {
Signal *s;
try {
s=getSignalByName(name);
}
catch (string e2) {
e << endl << tab << e2;
throw e.str();
}
if(s->getCycle() < 0) {
e << "signal " << name<< " doesn't have (yet?) a valid cycle";
throw e.str();
}
if(s->getCycle() > currentCycle_) {
ostringstream e;
e << "active cycle of signal " << name<< " is later than current cycle, cannot delay it";
throw e.str();
}
// update the lifeSpan of s
s->updateLifeSpan( currentCycle_ - s->getCycle() );
return s->delayedName( currentCycle_ - s->getCycle() );
}
else
return name;
}
void Operator::inPortMap(Operator* op, string componentPortName, string actualSignalName) throw(std::string) {
Signal* formal;
ostringstream e;
string name;
e << "ERROR in inPortMap(), "; // just in case
if(isSequential()) {
Signal *s;
try {
s=getSignalByName(actualSignalName);
}
catch (string e2) {
e << endl << tab << e2;
throw e.str();
}
if(s->getCycle() < 0) {
ostringstream e;
e << "signal " << actualSignalName<< " doesn't have (yet?) a valid cycle";
throw e.str();
}
if(s->getCycle() > currentCycle_) {
ostringstream e;
e << "active cycle of signal " << actualSignalName<< " is later than current cycle, cannot delay it";
throw e.str();
}
// update the lifeSpan of s
s->updateLifeSpan( currentCycle_ - s->getCycle() );
name = s->delayedName( currentCycle_ - s->getCycle() );
}
else
name = actualSignalName;
try {
formal=op->getSignalByName(componentPortName);
}
catch (string e2) {
e << endl << tab << e2;
throw e.str();
}
if (formal->type()!=Signal::in){
e << "signal " << componentPortName << " of component " << op->getName()
<< " doesn't seem to be an input port";
throw e.str();
}
// add the mapping to the mapping list of Op
op->portMap_[componentPortName] = name;
}