void display_module(std::ostream &out, const evl_modules &modules) {
for (evl_modules::const_iterator it1 = modules.begin(); it1 != modules.end(); ++it1) {
out << "module " << it1->name << " " << it1->c_wires.size() << " " << it1->c_components.size() << std::endl;
for(evl_wires::const_iterator it2 = it1->c_wires.begin(); it2 != it1->c_wires.end(); ++it2) {
out << "wire " << it2->first << " " << it2->second << std::endl;
}
for (evl_components::const_iterator it3 = it1->c_components.begin(); it3 != it1->c_components.end(); ++it3) {
out << "component " << it3->type << " " << it3->name << " " << it3->comp_pins.size() << std::endl;
for(evl_pins::const_iterator it4 = it3->comp_pins.begin(); it4 != it3->comp_pins.end(); ++it4) {
out << "pin " << it4->pin_name << " " << it4->msb << " " << it4->lsb << std::endl;
}
}
}
}
bool process_statements(evl_modules &modules, evl_statement &s) {
//assert(s.type == evl_statement::MODULE);
enum state_type {INIT, NAME, SEMI_CHECK, CHK_STMT, WIRE, COMPONENT, ENDMOD, DONE};
state_type state;
if (s.type == evl_statement::WIRE) {
state = WIRE;
}
else if (s.type == evl_statement::COMPONENT) {
state = COMPONENT;
}
if(i == 0) {
evl_module mod;
mod.name = "top";
modules.push_back(mod);
i++;
}
for (; !s.tokens.empty() && (state != DONE); s.tokens.pop_front()) {
evl_token t = s.tokens.front();
if (state == WIRE) {
evl_wires wires;
if (!process_wire_statements(wires,s)) {
return false;
}
else {
modules.back().c_wires.insert(wires.begin(), wires.end());
state = DONE;
break;
}
}
else if (state == COMPONENT) {
evl_components comp;
if (!process_component_statements(comp,s,modules.back().c_wires,modules.back().c_checkpoints)) {
return false;
}
else {
modules.back().c_components.splice(modules.back().c_components.end(),comp);
state = DONE;
break;
}
}
else {
//state = DONE;
assert(false); //never should get here
}
}
if (!s.tokens.empty() || (state != DONE)) {
std::cerr << "something wrong with the statement in mod" << std::endl;
return false;
}
return true;
}
//Module name and module number stored in a std::map
bool process_module_statements(evl_modules &modules, evl_statement &s) {
//assert(s.type == evl_statement::MODULE);
enum state_type {INIT, NAME, SEMI_CHECK, CHK_STMT, WIRE, COMPONENT, ENDMOD, DONE};
state_type state;
if(s.type == evl_statement::MODULE) {
state = INIT;
}
else if (s.type == evl_statement::ENDMODULE) {
state = ENDMOD;
}
else if (s.type == evl_statement::WIRE) {
state = WIRE;
}
else if (s.type == evl_statement::COMPONENT) {
state = COMPONENT;
}
for (; !s.tokens.empty() && (state != DONE); s.tokens.pop_front()) {
evl_token t = s.tokens.front();
if (state == INIT) {
if (t.type == evl_token::NAME && t.str == "module") {
state = NAME;
}
else {
std::cerr << "Need 'module' but found '" << t.str << "' at line " << t.line_no << std::endl;
return false;
}
}
else if (state == NAME) {
if (t.type == evl_token::NAME && t.str != "module") {
evl_module mod;
mod.name = t.str;
modules.push_back(mod);
state = SEMI_CHECK;
}
else {
std::cerr << "Need a NAME but found '" << t.str << "' at line " << t.line_no << std::endl;
return false;
}
}
else if (state == SEMI_CHECK) {
if (t.type == evl_token::SINGLE && t.str == ";") {
state = DONE;
}
else {
std::cerr << "Need a ';' but found '" << t.str << "' at line " << t.line_no << std::endl;
return false;
}
}
else if (state == WIRE) {
evl_wires wires;
if (!process_wire_statements(wires,s)) {
return false;
}
else {
modules.back().c_wires.insert(wires.begin(), wires.end());
state = DONE;
break;
}
}
else if (state == COMPONENT) {
evl_components comp;
if (!process_component_statements(comp,s,modules.back().c_wires)) {
return false;
}
else {
modules.back().c_components.splice(modules.back().c_components.end(),comp);
state = DONE;
break;
}
}
else if (state == ENDMOD) {
if(s.type == evl_statement::ENDMODULE) {
state = DONE;
}
}
else {
assert(false); //never should get here
}
}
if (!s.tokens.empty() || (state != DONE)) {
std::cerr << "something wrong with the statement in mod" << std::endl;
return false;
}
return true;
}
