ZTimerFreeglut::ZTimerFreeglut() : interval(25), started(false) { static int globalID = 0; while (mapTimers.find(globalID) != mapTimers.end()) { globalID++; } timerID = globalID; mapTimers[timerID] = this; }
static void _TimerFunc(int value) { hmap::iterator it = mapTimers.find(value); if (it == mapTimers.end()) return; ZTimerFreeglut* t = (*it).second; if (t->IsTimerStarted()) { glutTimerFunc(t->GetTimerInterval(), _TimerFunc, value); t->OnTimer(); } }
uint Synth::walk(DdNode *a_dd) { /** Walk given DdNode node (recursively). If a given node requires intermediate AND gates for its representation, the function adds them. Literal representing given input node is `not` added to the spec. :returns: literal representing input node **/ // caching static hmap<DdNode*, uint> cache; { auto cached_lit = cache.find(Cudd_Regular(a_dd)); if (cached_lit != cache.end()) return Cudd_IsComplement(a_dd) ? NEGATED(cached_lit->second) : cached_lit->second; } // end of caching if (Cudd_IsConstant(a_dd)) return (uint) (a_dd == cudd.bddOne().getNode()); // in aiger: 0 is False and 1 is True // get an index of the variable uint a_lit = aiger_by_cudd[Cudd_NodeReadIndex(a_dd)]; DdNode *t_bdd = Cudd_T(a_dd); DdNode *e_bdd = Cudd_E(a_dd); uint t_lit = walk(t_bdd); uint e_lit = walk(e_bdd); // ite(a_bdd, then_bdd, else_bdd) // = a*then + !a*else // = !(!(a*then) * !(!a*else)) // -> in general case we need 3 more ANDs uint a_t_lit = get_optimized_and_lit(a_lit, t_lit); uint na_e_lit = get_optimized_and_lit(NEGATED(a_lit), e_lit); uint n_a_t_lit = NEGATED(a_t_lit); uint n_na_e_lit = NEGATED(na_e_lit); uint and_lit = get_optimized_and_lit(n_a_t_lit, n_na_e_lit); uint res = NEGATED(and_lit); cache[Cudd_Regular(a_dd)] = res; if (Cudd_IsComplement(a_dd)) res = NEGATED(res); return res; }