void sadc_SetFIFOMode(int depth)
{
FIFOMode = _TRUE;
FIFODepth = depth;
ADC->SC4 = ADC_SC4_AFDEP(depth - 1); // The ADC module interprets a depth value of 1 as a 2 channel FIFO
}
/* ===================================================================*/
LDD_TDeviceData* ADC_Init(LDD_TUserData *UserDataPtr)
{
/* Allocate LDD device structure */
ADC_TDeviceDataPtr DeviceDataPrv;
uint8_t index; /* index to the internal buffer */
/* {MQXLite RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
DeviceDataPrv->UserData = UserDataPtr; /* Store the RTOS device structure */
for (index = 0U; index < ADC_MAX_HW_SAMPLE_COUNT; index++){
DeviceDataPrv->IntBuffer[index] = 0U; /* Initialization of the internal buffer */
}
/* SIM_SCGC: ADC=1 */
SIM_SCGC |= SIM_SCGC_ADC_MASK;
/* Enable device clock gate */
/* SIM_SCGC: ADC=1 */
SIM_SCGC |= SIM_SCGC_ADC_MASK;
/* Initialization of pin routing */
/* ADC_SC2: REFSEL=0 */
ADC_SC2 &= (uint32_t)~(uint32_t)(ADC_SC2_REFSEL(0x03));
/* ADC_APCTL1: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,ADPC=0x4001 */
ADC_APCTL1 = ADC_APCTL1_ADPC(0x4001);
/* ADC_SC3: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,ADLPC=0,ADIV=1,ADLSMP=0,MODE=2,ADICLK=0 */
ADC_SC3 = (ADC_SC3_ADIV(0x01) | ADC_SC3_MODE(0x02) | ADC_SC3_ADICLK(0x00));
/* ADC_SC2: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,ADACT=0,ADTRG=0,ACFE=0,ACFGT=0,FEMPTY=0,FFULL=0,REFSEL=0 */
ADC_SC2 = ADC_SC2_REFSEL(0x00);
/* ADC_SC4: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,HTRGME=0,??=0,ASCANE=0,ACFSEL=0,??=0,??=0,AFDEP=0 */
ADC_SC4 = ADC_SC4_AFDEP(0x00);
/* ADC_SC5: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,HTRGMASKE=0,HTRGMASKSEL=1 */
ADC_SC5 = ADC_SC5_HTRGMASKSEL_MASK;
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_ADC_ID,DeviceDataPrv);
return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the data data structure */
}
/*****************************************************************************//*!
*
* @brief FIFO Depth enables
*
* @param[in] pADC point to ADC module type.
* @param[in] u8FifoLevel set FIFO level.
*
* @return none
*
* @ Pass/ Fail criteria: none
*****************************************************************************/
void ADC_SetFifoLevel( ADC_Type *pADC, uint8_t u8FifoLevel )
{
uint32_t u32Temp;
u32Temp = pADC->SC4;
u32Temp &= ~ADC_SC4_AFDEP_MASK;
pADC->SC4 = u32Temp|ADC_SC4_AFDEP(u8FifoLevel);
}
