/***************************************************************************//** * @brief axiadc_idelay_set *******************************************************************************/ void axiadc_idelay_set(struct axiadc_state *st, unsigned lane, unsigned val) { if (PCORE_VERSION_MAJOR(st->pcore_version) > 8) { axiadc_write(st, ADI_REG_DELAY(lane), val); } else { axiadc_write(st, ADI_REG_DELAY_CNTRL, 0); axiadc_write(st, ADI_REG_DELAY_CNTRL, ADI_DELAY_ADDRESS(lane) | ADI_DELAY_WDATA(val) | ADI_DELAY_SEL); } }
/** * Set IO delay. * @param st The AXI ADC state structure. * @param lane Lane number. * @param val Value. * @param tx The Synthesizer TX = 1, RX = 0. * @return 0 in case of success, negative error code otherwise. */ static int32_t ad9361_iodelay_set(struct axiadc_state *st, unsigned lane, unsigned val, bool tx) { if (tx) { if (PCORE_VERSION_MAJOR(st->pcore_version) > 8) axiadc_write(st, 0x4000 + ADI_REG_DELAY(lane), val); else return -ENODEV; } else { axiadc_idelay_set(st, lane, val); } return 0; }