int main(int argc, char *argv[])
{
int ret = 0;
const float mclk_freq = 33.0f;
ADMXRC2_STATUS status;
ADMXRC2_CARD_INFO cardInfo;
ADMXRC2_SPACE_INFO spInfo;
ADMXRC2_BANK_INFO bankInfo, bankInfo2;
const char* filename;
Option options[8];
Arguments arguments;
float freq, min_freq, max_freq;
unsigned long i;
uint32_t sizeReg;
BOOLEAN dma;
BOOLEAN use64bit;
BOOLEAN speed;
unsigned long nrep;
BOOLEAN failed;
/* Set up expected options */
options[0].key = "banks";
options[0].type = Option_hex;
options[0].def.hexVal = 0xffffffff;
options[0].meaning = "bitmask of banks to test";
options[1].key = "card";
options[1].type = Option_uint;
options[1].def.uintVal = 0;
options[1].meaning = "ID of card to use";
options[2].key = "index";
options[2].type = Option_uint;
options[2].def.uintVal = 0;
options[2].meaning = "index of card to use";
options[3].key = "lclk";
options[3].type = Option_float;
options[3].def.floatVal = 33.0;
options[3].meaning = "local bus clock speed (MHz)";
options[4].key = "repeat";
options[4].type = Option_uint;
options[4].def.uintVal = 1;
options[4].meaning = "number of repetitions";
options[5].key = "speed";
options[5].type = Option_boolean;
options[5].def.booleanVal = TRUE;
options[5].meaning = "TRUE => measure access speed";
options[6].key = "usedma";
options[6].type = Option_boolean;
options[6].def.booleanVal = TRUE;
options[6].meaning = "TRUE => use 64 bit local bus";
options[7].key = "64";
options[7].type = Option_boolean;
options[7].def.booleanVal = FALSE;
options[7].meaning = "TRUE => use DMA for test";
arguments.nOption = 8;
arguments.option = options;
arguments.nParamType = 0;
arguments.minNParam = 0;
/* Parse command line */
parse_command_line("memtest", argc, argv, &arguments);
if (options[1].specified && options[2].specified) {
printf("*** Do not specify both /card and /index\n");
ret = -1;
goto done;
}
if (!options[2].specified) {
ADMXRC2_CARDID cardID = options[1].value.uintVal;
status = ADMXRC2_OpenCard(cardID, &card);
if (status != ADMXRC2_SUCCESS) {
printf("*** Failed to open card with ID %ld: %s\n",
(unsigned long) cardID, ADMXRC2_GetStatusString(status));
ret = -1;
goto done;
}
} else {
unsigned int index = options[2].value.uintVal;
status = ADMXRC2_OpenCardByIndex(index, &card);
if (status != ADMXRC2_SUCCESS) {
printf("*** Failed to open card with index %ld: %s\n",
(unsigned long) index, ADMXRC2_GetStatusString(status));
ret = -1;
goto done;
}
}
freq = options[3].value.floatVal;
nrep = options[4].value.uintVal;
speed = options[5].value.booleanVal;
dma = options[6].value.booleanVal;
use64bit = options[7].value.booleanVal;
/*
** Get card information, specifically for device fitted and
** number of SSRAM banks
*/
status = ADMXRC2_GetCardInfo(card, &cardInfo);
if (status != ADMXRC2_SUCCESS) {
printf("*** Failed to get card info: %s\n", ADMXRC2_GetStatusString(status));
return -1;
}
switch (cardInfo.BoardType) {
case ADMXRC2_BOARD_ADMXRC:
case ADMXRC2_BOARD_ADMXRC_P:
case ADMXRC2_BOARD_ADMXRC2_LITE:
min_freq = 25.0;
max_freq = 40.0;
break;
case ADMXRC2_BOARD_ADMXRC2:
min_freq = 24.0;
max_freq = 66.0;
break;
case ADMXRC2_BOARD_ADMXRC2_PRO_LITE:
min_freq = 24.0;
max_freq = 80.0;
break;
default:
printf("*** This example must be run on one of the following cards:\n\n");
printf("\tADM-XRC\n");
printf("\tADM-XRC-P\n");
printf("\tADM-XRCII-Lite\n");
printf("\tADM-XRCII\n");
printf("\tADM-XRCIIPro-Lite\n");
ret = -1;
goto done;
}
if (freq > max_freq || freq < min_freq) {
printf("*** LCLK frequency of %.1f MHz is not supported\n", freq);
ret = -1;
goto done;
}
if (use64bit && cardInfo.BoardType != ADMXRC2_BOARD_ADMXRC2_PRO_LITE) {
printf("*** 64-bit local bus is not supported on the specified card.\n");
ret = -1;
goto done;
}
/* Get the address of FPGA space */
status = ADMXRC2_GetSpaceInfo(card, 0, &spInfo);
if (status != ADMXRC2_SUCCESS) {
printf("Failed to get space 0 info: %s\n",
ADMXRC2_GetStatusString(status));
return -1;
}
fpgaSpace = (volatile uint32_t*) spInfo.VirtualBase;
if (!options[0].specified) {
bankTestMask = cardInfo.RAMBanksFitted;
} else {
bankTestMask = options[0].value.hexVal & cardInfo.RAMBanksFitted;
}
/*
** Check that the type, size, width etc. of each SSRAM bank
** is the same.
*/
numBank = 0;
testSize = 0;
for (i = 0; i < cardInfo.NumRAMBank; i++) {
status = ADMXRC2_GetBankInfo(card, i, &bankInfo2);
if (status != ADMXRC2_SUCCESS) {
printf("*** Failed to get bank %ld info: %s\n",
(unsigned long) i,
ADMXRC2_GetStatusString(status));
return -1;
}
if (!(bankInfo2.Type & (ADMXRC2_RAM_ZBTP | ADMXRC2_RAM_ZBTFT))) {
/* Ignore any banks that are not ZBT SSRAM */
continue;
}
if (!bankInfo2.Fitted) {
printf("*** Not all SSRAM banks are fitted - aborting.\n");
ret = -1;
goto done;
}
if (cardInfo.BoardType == ADMXRC2_BOARD_ADMXRC2_PRO_LITE && !use64bit) {
/*
** ADM-XPL ZBT bank width is 64 bits but the 32-bit version of design
** uses only the lower 32 bits of the ZBT bank.
*/
bankInfo2.Width = 32;
}
if (!numBank) {
memcpy(&bankInfo, &bankInfo2, sizeof(bankInfo));
bankSize = (bankInfo.Width / 8) * bankInfo.Size / 4;
} else {
if (bankInfo2.Type != bankInfo.Type ||
bankInfo2.Width != bankInfo.Width ||
bankInfo2.Size != bankInfo.Size) {
printf("*** Not all SSRAM banks are the same - aborting.\n");
ret = -1;
goto done;
}
}
numBank++;
if (bankTestMask & (0x1UL << i)) {
testSize += (bankInfo.Width / 8) * bankInfo.Size / 4;
}
}
if (!numBank) {
printf("*** No SSRAM banks found - aborting.\n");
ret = -1;
goto done;
}
/*
** Calculate memory size in longwords (32-bit words)
*/
memorySize = numBank * bankSize;
lastPageSize = memorySize & (pageSize - 1);
/*
** Determine value to program into the SIZE register in the FPGA
*/
switch (bankInfo.Size) {
case 128*1024:
sizeReg = 0;
break;
case 256*1024:
sizeReg = 1;
break;
case 512*1024:
sizeReg = 2;
break;
case 1024*1024:
sizeReg = 3;
break;
default:
printf("*** SSRAM of %ld words x %ld is not supported by this application\n",
(unsigned long) bankInfo.Size, (unsigned long) bankInfo.Width);
ret = -1;
goto done;
}
ssram = (volatile uint32_t*) (((uint8_t*) fpgaSpace) + ssramOffset);
rambuf = (uint32_t*) ADMXRC2_Malloc(memorySize * sizeof(uint32_t));
if (rambuf == NULL) {
printf("*** Failed to allocate RAM buffer - aborting\n");
ret = -1;
goto done;
}
chkbuf = (uint32_t*) ADMXRC2_Malloc(memorySize * sizeof(uint32_t));
if (chkbuf == NULL) {
printf("*** Failed to allocate RAM readback buffer - aborting\n");
ret = -1;
goto done;
}
status = ADMXRC2_SetClockRate(card, ADMXRC2_CLOCK_LCLK, freq * 1.0e6, NULL);
if (status != ADMXRC2_SUCCESS) {
printf("*** Failed to set LCLK to %.1fMHz: %s\n",
freq, ADMXRC2_GetStatusString(status));
ret = -1;
goto done;
}
if (cardInfo.BoardType != ADMXRC2_BOARD_ADMXRC2_PRO_LITE) {
status = ADMXRC2_SetClockRate(card, 1, mclk_freq * 1.0e6, NULL);
if (status != ADMXRC2_SUCCESS) {
printf("*** Failed to set clock 1 to %.1fMHz: %s\n",
mclk_freq, ADMXRC2_GetStatusString(status));
return -1;
}
}
filename="/var/www/html/VirtualLabs/experiments/exp_3/bitfiles/user_configuration.bit";
status = ADMXRC2_ConfigureFromFile(card, filename);
if (status != ADMXRC2_SUCCESS) {
printf ("*** Failed to load the bitstream '%s': %s\n",
filename, ADMXRC2_GetStatusString(status));
return -1;
}
if (use64bit) {
uint32_t config;
config = ADMXRC2_SPACE_SET_WIDTH | ADMXRC2_SPACE_WIDTH_64;
status = ADMXRC2_SetSpaceConfig(card, 0, config);
if (status != ADMXRC2_SUCCESS) {
printf ("*** Failed to set space configuration: %s\n",
ADMXRC2_GetStatusString(status));
return -1;
}
}
status = ADMXRC2_SetupDMA(card,
rambuf,
memorySize * sizeof(uint32_t),
0,
&dmaDesc1);
if (status != ADMXRC2_SUCCESS) {
printf ("*** Failed to get a DMA descriptor: %s\n",
ADMXRC2_GetStatusString(status));
return -1;
}
status = ADMXRC2_SetupDMA(card,
chkbuf,
memorySize * sizeof(uint32_t),
0,
&dmaDesc2);
if (status != ADMXRC2_SUCCESS) {
printf ("*** Failed to get a DMA descriptor: %s\n",
ADMXRC2_GetStatusString(status));
return -1;
}
dmaMode = ADMXRC2_BuildDMAModeWord(cardInfo.BoardType,
use64bit ? ADMXRC2_IOWIDTH_64 : ADMXRC2_IOWIDTH_32,
0,
ADMXRC2_DMAMODE_USEREADY | ADMXRC2_DMAMODE_USEBTERM | ADMXRC2_DMAMODE_BURSTENABLE);
/* Wait for DLLs/DCMs to lock */
sleep(1);
fpgaSpace[ZBT_SIZE_REG] = sizeReg;
fpgaSpace[ZBT_SIZE_REG]; /* make sure it's got there */
//Set the FPGA to pipelined mode
fpgaSpace[ZBT_PIPELINE_REG] = 0x1;
fpgaSpace[ZBT_PIPELINE_REG]; /* make sure it's got there */
//printf("\n\t Dmamode\t%08X",dmaMode);
failed = FALSE;
unsigned long j, k;
uint32_t exp, act;
unsigned long rep;
if (!failed) {
//rambuf_8 = rambuf;
for (j = 0; j < bankSize; j++) {
rambuf[j] = j;
rambuf[j+2*bankSize] = 262143 - j;
rambuf[j+4*bankSize] = 0x12348765;
}
status = writeSSRAM(rambuf, 0, 6*bankSize, dma);
if (status != ADMXRC2_SUCCESS) {
printf("Error: failed to write SSRAM\n");
failed = TRUE;
}
fpgaSpace[6] = os_cpu_to_le32(1);
fpgaSpace[6];
while(fpgaSpace[7]!=os_cpu_to_le32(0x31));
fpgaSpace[6] = os_cpu_to_le32(0);
fpgaSpace[6];
}
for (j = 0; j < numBank; j++) {
for (k = 0; k < bankSize; k++) {
unsigned long idx = j * bankSize + k;
chkbuf[idx] = 0;
}
}
status = readSSRAM(chkbuf, 0,6*bankSize, dma);
if (status != ADMXRC2_SUCCESS) {
printf("Error: failed to read SSRAM\n");
failed = TRUE;
}
printf("\nData written onto the banks\n");
for (j = 0;j < 20;j++){
printf("\n%02d %08X %08X %08X %08X %08X %08X ", j,rambuf[j],rambuf[1*bankSize+j],rambuf[2*bankSize+j],rambuf[3*bankSize+j],rambuf[4*bankSize+j],rambuf[5*bankSize+j]);
}
printf("\n\nData read from all the banks\n");
for (j = 0;j < 20;j++){
printf("\n%02d %08X %08X %08X %08X %08X %08X ", j,chkbuf[j],chkbuf[1*bankSize+j],chkbuf[2*bankSize+j],chkbuf[3*bankSize+j],chkbuf[4*bankSize+j],chkbuf[5*bankSize+j]);
}
if (failed){
printf("*** FAILED***\n");
goto done;
}
done:
if (rambuf != NULL) {
ADMXRC2_Free(rambuf);
}
if (chkbuf != NULL) {
ADMXRC2_Free(chkbuf);
}
if (dmaDesc1Valid) {
ADMXRC2_UnsetupDMA(card, dmaDesc1);
}
if (dmaDesc2Valid) {
ADMXRC2_UnsetupDMA(card, dmaDesc2);
}
if (card != ADMXRC2_HANDLE_INVALID_VALUE) {
ADMXRC2_CloseCard(card);
}
return ret;
}
int main(int argc, char *argv[])
{
int ret = 0;
const float mclk_freq = 33.0f;
ADMXRC2_STATUS status;
ADMXRC2_CARD_INFO cardInfo;
ADMXRC2_SPACE_INFO spInfo;
ADMXRC2_BANK_INFO bankInfo, bankInfo2;
const char* filename;
Option options[8];
Arguments arguments;
float freq, min_freq, max_freq;
unsigned long i;
uint32_t sizeReg;
BOOLEAN dma;
BOOLEAN use64bit;
BOOLEAN speed;
unsigned long nrep;
BOOLEAN failed;
/* Set up expected options */
options[0].key = "banks";
options[0].type = Option_hex;
options[0].def.hexVal = 0xffffffff;
options[0].meaning = "bitmask of banks to test";
options[1].key = "card";
options[1].type = Option_uint;
options[1].def.uintVal = 0;
options[1].meaning = "ID of card to use";
options[2].key = "index";
options[2].type = Option_uint;
options[2].def.uintVal = 0;
options[2].meaning = "index of card to use";
options[3].key = "lclk";
options[3].type = Option_float;
options[3].def.floatVal = 33.0;
options[3].meaning = "local bus clock speed (MHz)";
options[4].key = "repeat";
options[4].type = Option_uint;
options[4].def.uintVal = 1;
options[4].meaning = "number of repetitions";
options[5].key = "speed";
options[5].type = Option_boolean;
options[5].def.booleanVal = TRUE;
options[5].meaning = "TRUE => measure access speed";
options[6].key = "usedma";
options[6].type = Option_boolean;
options[6].def.booleanVal = TRUE;
options[6].meaning = "TRUE => use DMA transfers";
options[7].key = "64";
options[7].type = Option_boolean;
options[7].def.booleanVal = FALSE;
options[7].meaning = "TRUE => use 64-bit local bus";
arguments.nOption = 8;
arguments.option = options;
arguments.nParamType = 0;
arguments.minNParam = 0;
/* Parse command line */
parse_command_line("memtest", argc, argv, &arguments);
if (options[1].specified && options[2].specified) {
printf("*** Do not specify both /card and /index\n");
ret = -1;
//goto done;
}
if (!options[2].specified) {
ADMXRC2_CARDID cardID = options[1].value.uintVal;
status = ADMXRC2_OpenCard(cardID, &card);
if (status != ADMXRC2_SUCCESS) {
printf("*** Failed to open card with ID %ld: %s\n",
(unsigned long) cardID, ADMXRC2_GetStatusString(status));
ret = -1;
//goto done;
}
} else {
unsigned int index = options[2].value.uintVal;
status = ADMXRC2_OpenCardByIndex(index, &card);
if (status != ADMXRC2_SUCCESS) {
printf("*** Failed to open card with index %ld: %s\n",
(unsigned long) index, ADMXRC2_GetStatusString(status));
ret = -1;
// goto done;
}
}
freq = options[3].value.floatVal;
nrep = options[4].value.uintVal;
speed = options[5].value.booleanVal;
dma = options[6].value.booleanVal;
use64bit = options[7].value.booleanVal;
/*
** Find out if we're running on a big-endian machine
*/
bBigEndian = (os_cpu_to_le32(0x1U) != 0x1U);
/*
** Get card information, specifically for device fitted and
** number of SSRAM banks
*/
status = ADMXRC2_GetCardInfo(card, &cardInfo);
if (status != ADMXRC2_SUCCESS) {
printf("*** Failed to get card info: %s\n", ADMXRC2_GetStatusString(status));
return -1;
}
switch (cardInfo.BoardType) {
case ADMXRC2_BOARD_ADMXRC:
case ADMXRC2_BOARD_ADMXRC_P:
case ADMXRC2_BOARD_ADMXRC2_LITE:
min_freq = 25.0;
max_freq = 40.0;
break;
case ADMXRC2_BOARD_ADMXRC2:
case ADMXRC2_BOARD_ADMXRC4LS:
case ADMXRC2_BOARD_ADMXRC4LX:
case ADMXRC2_BOARD_ADMXRC4SX:
min_freq = 24.0;
max_freq = 66.0;
break;
case ADMXRC2_BOARD_ADMXPL:
min_freq = 24.0;
max_freq = 80.0;
break;
default:
printf("*** This example must be run on one of the following cards:\n\n");
printf("\tADM-XRC\n");
printf("\tADM-XRC-P\n");
printf("\tADM-XRCII-Lite\n");
printf("\tADM-XRCII\n");
printf("\tADM-XPL\n");
printf("\tADM-XRC4LX\n");
printf("\tADM-XRC4SX\n");
ret = -1;
//goto done;
}
if (freq > max_freq || freq < min_freq) {
printf("*** LCLK frequency of %.1f MHz is not supported\n", freq);
ret = -1;
// goto done;
}
if (use64bit && cardInfo.BoardType != ADMXRC2_BOARD_ADMXPL) {
printf("*** 64-bit local bus is not supported on the specified card.\n");
ret = -1;
//goto done;
}
/* Get the address of FPGA space */
status = ADMXRC2_GetSpaceInfo(card, 0, &spInfo);
if (status != ADMXRC2_SUCCESS) {
printf("Failed to get space 0 info: %s\n",
ADMXRC2_GetStatusString(status));
return -1;
}
fpgaSpace = (volatile uint32_t*) spInfo.VirtualBase;
fpgaSpace[6] = os_cpu_to_le32(0);
fpgaSpace[6];
fpgaSpace[7] = os_cpu_to_le32(0);
fpgaSpace[7];
if (!options[0].specified) {
bankTestMask = cardInfo.RAMBanksFitted;
} else {
bankTestMask = options[0].value.hexVal & cardInfo.RAMBanksFitted;
}
/*
** Check that the type, size, width etc. of each SSRAM bank
** is the same.
*/
numBank = 0;
testSize = 0;
for (i = 0; i < cardInfo.NumRAMBank; i++) {
status = ADMXRC2_GetBankInfo(card, i, &bankInfo2);
if (status != ADMXRC2_SUCCESS) {
printf("*** Failed to get bank %ld info: %s\n",
(unsigned long) i,
ADMXRC2_GetStatusString(status));
return -1;
}
if (!(bankInfo2.Type & (ADMXRC2_RAM_ZBTP | ADMXRC2_RAM_ZBTFT))) {
/* Ignore any banks that are not ZBT SSRAM */
continue;
}
if (!bankInfo2.Fitted) {
printf("*** Not all SSRAM banks are fitted - aborting.\n");
ret = -1;
//goto done;
}
if (cardInfo.BoardType == ADMXRC2_BOARD_ADMXPL && !use64bit) {
/*
** ADM-XPL ZBT bank width is 64 bits but the 32-bit version of design
** uses only the lower 32 bits of the ZBT bank.
*/
bankInfo2.Width = 32;
}
if (!numBank) {
memcpy(&bankInfo, &bankInfo2, sizeof(bankInfo));
bankSize = (bankInfo.Width / 8) * bankInfo.Size;
} else {
if (bankInfo2.Type != bankInfo.Type ||
bankInfo2.Width != bankInfo.Width ||
bankInfo2.Size != bankInfo.Size) {
printf("*** Not all SSRAM banks are the same - aborting.\n");
ret = -1;
//goto done;
}
}
numBank++;
if (bankTestMask & (0x1UL << i)) {
testSize += (bankInfo.Width / 8) * bankInfo.Size;
}
}
if (!numBank) {
printf("*** No SSRAM banks found - aborting.\n");
ret = -1;
//goto done;
}
/*
** Calculate memory size in bytes
*/
memorySize = numBank * bankSize;
lastPageSize = memorySize & (pageSize - 1);
/*
** Determine value to program into the SIZE register in the FPGA
*/
switch (bankInfo.Size) {
case 128*1024:
sizeReg = 0;
break;
case 256*1024:
sizeReg = 1;
break;
case 512*1024:
sizeReg = 2;
break;
case 1024*1024:
sizeReg = 3;
break;
case 2048*1024:
sizeReg = 4;
break;
default:
printf("*** SSRAM of %ld words x %ld is not supported by this application\n",
(unsigned long) bankInfo.Size, (unsigned long) bankInfo.Width);
ret = -1;
//goto done;
}
ssram = (volatile uint32_t*) (((uint8_t*) fpgaSpace) + ssramOffset);
rambuf = (uint8_t*) ADMXRC2_Malloc(memorySize);
if (rambuf == NULL) {
printf("*** Failed to allocate RAM buffer - aborting\n");
ret = -1;
//goto done;
}
rambuf32 = (uint32_t*) rambuf;
chkbuf = (uint8_t*) ADMXRC2_Malloc(memorySize);
if (chkbuf == NULL) {
printf("*** Failed to allocate RAM readback buffer - aborting\n");
ret = -1;
///goto done;
}
chkbuf32 = (uint32_t*) chkbuf;
status = ADMXRC2_SetClockRate(card, ADMXRC2_CLOCK_LCLK, freq * 1.0e6, NULL);
if (status != ADMXRC2_SUCCESS) {
printf("*** Failed to set LCLK to %.1fMHz: %s\n",
freq, ADMXRC2_GetStatusString(status));
ret = -1;
//goto done;
}
if (cardInfo.BoardType != ADMXRC2_BOARD_ADMXPL) {
status = ADMXRC2_SetClockRate(card, 1, mclk_freq * 1.0e6, NULL);
if (status != ADMXRC2_SUCCESS) {
printf("*** Failed to set clock 1 to %.1fMHz: %s\n",
mclk_freq, ADMXRC2_GetStatusString(status));
return -1;
}
}
filename="/var/www/html/VirtualLabs/experiments/exp_4/bitfiles/user_configuration.bit";
status = ADMXRC2_ConfigureFromFile(card, filename);
if (status != ADMXRC2_SUCCESS) {
printf ("*** Failed to load the bitstream '%s': %s\n",
filename, ADMXRC2_GetStatusString(status));
return -1;
}
if (use64bit) {
uint32_t config;
config = ADMXRC2_SPACE_SET_WIDTH | ADMXRC2_SPACE_WIDTH_64;
status = ADMXRC2_SetSpaceConfig(card, 0, config);
if (status != ADMXRC2_SUCCESS) {
printf ("*** Failed to set space configuration: %s\n",
ADMXRC2_GetStatusString(status));
return -1;
}
}
status = ADMXRC2_SetupDMA(card,
rambuf,
memorySize,
0,
&dmaDesc1);
if (status != ADMXRC2_SUCCESS) {
printf ("*** Failed to get a DMA descriptor: %s\n",
ADMXRC2_GetStatusString(status));
return -1;
}
status = ADMXRC2_SetupDMA(card,
chkbuf,
memorySize,
0,
&dmaDesc2);
if (status != ADMXRC2_SUCCESS) {
printf ("*** Failed to get a DMA descriptor: %s\n",
ADMXRC2_GetStatusString(status));
return -1;
}
dmaMode = ADMXRC2_BuildDMAModeWord(cardInfo.BoardType,
use64bit ? ADMXRC2_IOWIDTH_64 : ADMXRC2_IOWIDTH_32,
0,
ADMXRC2_DMAMODE_USEREADY | ADMXRC2_DMAMODE_USEBTERM | ADMXRC2_DMAMODE_BURSTENABLE);
/* Wait for DLLs/DCMs to lock */
sleep(1);
/*
** Program the number of address bits used by the SSRAMs
*/
fpgaSpace[ZBT_SIZE_REG] = os_cpu_to_le32(sizeReg);
fpgaSpace[ZBT_SIZE_REG]; /* make sure it's got there */
printf("Size reg = 0x%8.8lx\n", (unsigned long) os_le32_to_cpu(fpgaSpace[ZBT_SIZE_REG]));
printf("Info reg = 0x%8.8lx\n", (unsigned long) os_le32_to_cpu(fpgaSpace[ZBT_INFO_REG]));
printf("Status reg = 0x%8.8lx\n", (unsigned long) os_le32_to_cpu(fpgaSpace[ZBT_STATUS_REG]));
failed = FALSE;
// printf("Performing memory tests using %s\n",
// dma ? "DMA" : "programmed I/O");
/* Iterate over flowthrough and pipelined */
for (i = 0; i < 2; i++) {
int nError = 0;
unsigned long j, k;
uint32_t exp, act;
unsigned long rep;
if (i == 0) {
if (!(bankInfo.Type & ADMXRC2_RAM_ZBTFT)) {
continue;
}
/*
** Set the FPGA to flowthrough mode
*/
fpgaSpace[ZBT_PIPELINE_REG] = os_cpu_to_le32(0x0);
fpgaSpace[ZBT_PIPELINE_REG]; /* make sure it's got there */
// printf("Testing %ld kB in flowthrough mode...\n", testSize / 1024);
} else {
if (!(bankInfo.Type & ADMXRC2_RAM_ZBTP)) {
continue;
}
/*
** Set the FPGA to pipelined mode
*/
fpgaSpace[ZBT_PIPELINE_REG] = os_cpu_to_le32(0x1);
fpgaSpace[ZBT_PIPELINE_REG]; /* make sure it's got there */
printf("Testing %ld kB in pipelined mode...\n", testSize / 1024);
}
}
//////////////////////////////////////////////////////////////////////////////////////////////////////////
FILE *fptr;
char filen[30];
char initial[16];
char temp[16];
argc --;
if(argc > 0)
strcpy(filen,*(argv+1));
else
{
printf(" Image file name not specified \n");
exit(1);
}
if(!(fptr = fopen(filen,"r")))
{
printf(" Image file does not exist specify some other existing image file \n");
exit(1);
}
int row=0,col=0,count =0,j;
int header =0;
char ch;
while( count!=3)
{
count ++;
ch=fgetc(fptr);
initial[header]=ch;
header++;
}
ch=fgetc(fptr);
initial[header]=ch;
header++;
while(ch!=32)
{
col= col*10+ (ch-48) ;
ch = fgetc(fptr);
initial[header]=ch;
header++;
}
ch= fgetc(fptr);
initial[header]=ch;
header++;
while(ch!=10)
{
row = row*10 + (ch-48);
ch= fgetc(fptr);
initial[header]=ch;
header++;
}
count =0;
while( count!=4)
{
count ++;
ch=fgetc(fptr);
initial[header]=ch;
header++;
}
initial[header]='\0';
// printf( "\n row === %d",row);
// printf( "\n col === %d",col);
strcpy(temp,initial);
// printf( "\n header len === %d",header);
// printf( "\n Header === %s======%s",initial,temp);
int matrix[row][col];
for(i=0;i< row;i++)
{
for( j= 0;j< col;j++)
matrix[i][j]=fgetc(fptr);
}
fclose(fptr);
int output[row][col];
int m,n;
count = 0;
for(m=0;m<row;m++)
{for(n=0;n<col;n++)
{ output[m][n]=0;
rambuf[count] = matrix[m][n];
count++;}
}
count = 0;
for(j=0;j<2;j++)
{
status = writeSSRAM(rambuf + j * bankSize, j * bankSize, bankSize, dma);
if (status != ADMXRC2_SUCCESS) {
printf("Error: failed to write SSRAM\n");
failed = TRUE;
}
}
fpgaSpace[6] = os_cpu_to_le32(1);
fpgaSpace[6];
while(fpgaSpace[7]!=os_cpu_to_le32(0x31));
fpgaSpace[6] = os_cpu_to_le32(0);
fpgaSpace[6];
sleep(10);
if (!failed) {
for (j = 0; j < 2; j++) {
if (!(bankTestMask & (1U << j))) {
continue;
}
status = readSSRAM(chkbuf + j * bankSize, j * bankSize, bankSize, dma);
if (status != ADMXRC2_SUCCESS) {
printf("Error: failed to read SSRAM\n");
failed = TRUE;
break;
}
}
}
count = 0;
for(m=0;m<row;m++)
{for(n=0;n<col;n++)
{ output[m][n]=chkbuf[count];
count++;}
}
//=========================================== new IMAGE FILE BUILD============================
char newFile[] = "Converted_Imag";
char *newfile= strncat(newFile,".pgm",4);
fptr = fopen(newfile,"w");
count=0;
// strcpy(initial,temp);
printf("\n %s..... %s\n",initial,temp);
while(count!=15)
{
fputc(initial[count],fptr);
count++;
}
for(i=0;i< row;i++)
{
for( j= 0;j< col;j++)
fputc(output[i][j],fptr);
}
fclose(fptr);
////////////////////////////////////////////////////////////////////////////////////////////////////////////
if (speed) {
/*
** Measure the host read and host write speeds of the SSRAM,
** using DMA.
*/
float bytes, rate;
double delta;
struct timeval start, now, elapsed;
printf("Measuring access speed...\n");
start = get_time();
bytes = 0.0f;
do {
readSSRAM(rambuf, 0, memorySize, dma);
bytes += (float) memorySize;
now = get_time();
elapsed = time_subtract(&now, &start);
delta = time_to_double(&elapsed);
} while (delta < 2.0);
rate = bytes / delta;
printf("SSRAM to host throughput = %.1fMB/s\n", rate / 1048576.0f);
start = get_time();
bytes = 0.0f;
do {
writeSSRAM(rambuf, 0, memorySize, dma);
bytes += (float) memorySize;
now = get_time();
elapsed = time_subtract(&now, &start);
delta = time_to_double(&elapsed);
} while (delta < 2.0);
rate = bytes / delta;
printf("Host to SSRAM throughput = %.1fMB/s\n", rate / 1048576.0f);
}
ADMXRC2_Free (rambuf);
ADMXRC2_Free (chkbuf);
ADMXRC2_CloseCard (card);
exit(0);
return 0;
}
int main(int argc, char *argv[])
{
int ret = 0;
const float mclk_freq = 33.0f;
ADMXRC2_STATUS status;
ADMXRC2_CARD_INFO cardInfo;
ADMXRC2_SPACE_INFO spInfo;
ADMXRC2_BANK_INFO bankInfo, bankInfo2;
const char* filename;
Option options[8];
Arguments arguments;
float freq, min_freq, max_freq;
unsigned long i;
uint32_t sizeReg;
BOOLEAN dma;
BOOLEAN use64bit;
BOOLEAN speed;
unsigned long nrep;
BOOLEAN failed;
/* Set up expected options */
options[0].key = "banks";
options[0].type = Option_hex;
options[0].def.hexVal = 0xffffffff;
options[0].meaning = "bitmask of banks to test";
options[1].key = "card";
options[1].type = Option_uint;
options[1].def.uintVal = 0;
options[1].meaning = "ID of card to use";
options[2].key = "index";
options[2].type = Option_uint;
options[2].def.uintVal = 0;
options[2].meaning = "index of card to use";
options[3].key = "lclk";
options[3].type = Option_float;
options[3].def.floatVal = 33.0;
options[3].meaning = "local bus clock speed (MHz)";
options[4].key = "repeat";
options[4].type = Option_uint;
options[4].def.uintVal = 1;
options[4].meaning = "number of repetitions";
options[5].key = "speed";
options[5].type = Option_boolean;
options[5].def.booleanVal = TRUE;
options[5].meaning = "TRUE => measure access speed";
options[6].key = "usedma";
options[6].type = Option_boolean;
options[6].def.booleanVal = TRUE;
options[6].meaning = "TRUE => use 64 bit local bus";
options[7].key = "64";
options[7].type = Option_boolean;
options[7].def.booleanVal = FALSE;
options[7].meaning = "TRUE => use DMA for test";printf("Writing 0xAAAAAAAA...\n");
arguments.nOption = 8;
arguments.option = options;
arguments.nParamType = 0;
arguments.minNParam = 0;
/* Parse command line */
parse_command_line("memtest", argc, argv, &arguments);
status = ADMXRC2_OpenCardByIndex(index, &card);
if (status != ADMXRC2_SUCCESS) {
printf("*** Failed to open card with index %ld: %s\n",
(unsigned long) index, ADMXRC2_GetStatusString(status));
ret = -1;
goto done;
}
freq = options[3].value.floatVal;
nrep = options[4].value.uintVal;
speed = options[5].value.booleanVal;
dma = options[6].value.booleanVal;
use64bit = options[7].value.booleanVal;
/*
** Get card information, specifically for device fitted and
** number of SSRAM banks
*/
status = ADMXRC2_GetCardInfo(card, &cardInfo);
if (status != ADMXRC2_SUCCESS) {
printf("*** Failed to get card info: %s\n", ADMXRC2_GetStatusString(status));
return -1;
}
/* Get the address of FPGA space */
status = ADMXRC2_GetSpaceInfo(card, 0, &spInfo);
if (status != ADMXRC2_SUCCESS) {
printf("Failed to get space 0 info: %s\n",
ADMXRC2_GetStatusString(status));
return -1;
}
fpgaSpace = (volatile uint32_t*) spInfo.VirtualBase;
if (!options[0].specified) {
bankTestMask = cardInfo.RAMBanksFitted;
} else {
bankTestMask = options[0].value.hexVal & cardInfo.RAMBanksFitted;
}
/*
** Check that the type, size, width etc. of each SSRAM bank
** is the same.
*/
numBank = 0;
testSize = 0;
for (i = 0; i < cardInfo.NumRAMBank; i++) {
status = ADMXRC2_GetBankInfo(card, i, &bankInfo2);
if (status != ADMXRC2_SUCCESS) {
printf("*** Failed to get bank %ld info: %s\n",
(unsigned long) i,
ADMXRC2_GetStatusString(status));
return -1;
}
if (!(bankInfo2.Type & (ADMXRC2_RAM_ZBTP | ADMXRC2_RAM_ZBTFT))) {
/* Ignore any banks that are not ZBT SSRAM */
continue;
}
if (!bankInfo2.Fitted) {
printf("*** Not all SSRAM banks are fitted - aborting.\n");
ret = -1;
goto done;
}
if (!numBank) {
memcpy(&bankInfo, &bankInfo2, sizeof(bankInfo));
bankSize = (bankInfo.Width / 8) * bankInfo.Size / 4;
} else {
if (bankInfo2.Type != bankInfo.Type ||
bankInfo2.Width != bankInfo.Width ||
bankInfo2.Size != bankInfo.Size) {
printf("*** Not all SSRAM banks are the same - aborting.\n");
ret = -1;
goto done;
}
}
numBank++;
if (bankTestMask & (0x1UL << i)) {
testSize += (bankInfo.Width / 8) * bankInfo.Size / 4;
}
}
if (!numBank) {
printf("*** No SSRAM banks found - aborting.\n");
ret = -1;
goto done;
}
/*
** Calculate memory size in longwords (32-bit words)
*/
memorySize = numBank * bankSize;
lastPageSize = memorySize & (pageSize - 1);
/*
** Determine value to program into the SIZE register in the FPGA
*/
switch (bankInfo.Size) {
case 128*1024:
sizeReg = 0;
break;
case 256*1024:
sizeReg = 1;
break;
case 512*1024:
sizeReg = 2;
break;
case 1024*1024:
sizeReg = 3;
break;
default:
printf("*** SSRAM of %ld words x %ld is not supported by this application\n",
(unsigned long) bankInfo.Size, (unsigned long) bankInfo.Width);
ret = -1;
goto done;
}
ssram = (volatile uint32_t*) (((uint8_t*) fpgaSpace) + ssramOffset);
rambuf = (uint32_t*) ADMXRC2_Malloc(memorySize * sizeof(uint32_t));
if (rambuf == NULL) {
printf("*** Failed to allocate RAM buffer - aborting\n");
ret = -1;
goto done;
}
chkbuf = (uint32_t*) ADMXRC2_Malloc(memorySize * sizeof(uint32_t));
if (chkbuf == NULL) {
printf("*** Failed to allocate RAM readback buffer - aborting\n");
ret = -1;
goto done;
}
status = ADMXRC2_SetClockRate(card, ADMXRC2_CLOCK_LCLK, freq * 1.0e6, NULL);
if (status != ADMXRC2_SUCCESS) {
printf("*** Failed to set LCLK to %.1fMHz: %s\n",
freq, ADMXRC2_GetStatusString(status));
ret = -1;
goto done;
}
if (cardInfo.BoardType != ADMXRC2_BOARD_ADMXRC2_PRO_LITE) {
status = ADMXRC2_SetClockRate(card, 1, mclk_freq * 1.0e6, NULL);
if (status != ADMXRC2_SUCCESS) {
printf("*** Failed to set clock 1 to %.1fMHz: %s\n",
mclk_freq, ADMXRC2_GetStatusString(status));
return -1;
}
}
if (use64bit) {
uint32_t config;
config = ADMXRC2_SPACE_SET_WIDTH | ADMXRC2_SPACE_WIDTH_64;
status = ADMXRC2_SetSpaceConfig(card, 0, config);
if (status != ADMXRC2_SUCCESS) {
printf ("*** Failed to set space configuration: %s\n",
ADMXRC2_GetStatusString(status));
return -1;
}
}
status = ADMXRC2_SetupDMA(card,
rambuf,
memorySize * sizeof(uint32_t),
0,
&dmaDesc1);
if (status != ADMXRC2_SUCCESS) {
printf ("*** Failed to get a DMA descriptor: %s\n",
ADMXRC2_GetStatusString(status));
return -1;
}
status = ADMXRC2_SetupDMA(card,
chkbuf,
memorySize * sizeof(uint32_t),
0,
&dmaDesc2);
if (status != ADMXRC2_SUCCESS) {
printf ("*** Failed to get a DMA descriptor: %s\n",
ADMXRC2_GetStatusString(status));
return -1;
}
dmaMode = ADMXRC2_BuildDMAModeWord(cardInfo.BoardType,
use64bit ? ADMXRC2_IOWIDTH_64 : ADMXRC2_IOWIDTH_32,
0,
ADMXRC2_DMAMODE_USEREADY | ADMXRC2_DMAMODE_USEBTERM | ADMXRC2_DMAMODE_BURSTENABLE);
/* Wait for DLLs/DCMs to lock */
sleep(1);
/*
** Program the number of address bits used by the SSRAMs
*/
fpgaSpace[ZBT_SIZE_REG] = sizeReg;
fpgaSpace[ZBT_SIZE_REG]; /* make sure it's got there */
printf("Size reg = 0x%8.8lx\n", (unsigned long) fpgaSpace[ZBT_SIZE_REG]);
printf("Info reg = 0x%8.8lx\n", (unsigned long) fpgaSpace[ZBT_INFO_REG]);
printf("Status reg = 0x%8.8lx\n", (unsigned long) fpgaSpace[ZBT_STATUS_REG]);
failed = FALSE;
/* Iterate over flowthrough and pipelined */
for (i = 0; i < 2; i++) {
int nError = 0;
unsigned long j, k;
//char m= 'a';
uint32_t exp, act;
unsigned long rep;
if (i == 0) {
if (!(bankInfo.Type & ADMXRC2_RAM_ZBTFT)) {
continue;
}
/*
** Set the FPGA to flowthrough mode
*/
fpgaSpace[ZBT_PIPELINE_REG] = 0x0;
fpgaSpace[ZBT_PIPELINE_REG]; /* make sure it's got there */
printf("Testing %ld kB in flowthrough mode...\n", testSize * 4 / 1024);
} else {
if (!(bankInfo.Type & ADMXRC2_RAM_ZBTP)) {
continue;
}
/*
** Set the FPGA to pipelined mode
*/
fpgaSpace[ZBT_PIPELINE_REG] = 0x1;
fpgaSpace[ZBT_PIPELINE_REG]; /* make sure it's got there */
printf("Testing %ld kB in pipelined mode...\n", testSize * 4 / 1024);
}
for (rep = 0; rep < nrep; rep++) {
printf("Repetition %ld\n", rep);
///////////////////////////////////////////STARTING//////////////////////////////////////
/* Perform 0xAAAAAAA test - look for shorted/stuck data pins */
if (!failed && nError == 0) {
rambuf_8 = rambuf;
for (j = 0; j < 50; j++) {
rambuf_8[j+12*bankSize] = j;
}
for (j = 0; j < 50; j++) {
rambuf[j+4*bankSize] = 0;
}
status = writeSSRAM(rambuf, 3 * bankSize, bankSize, dma);
if (status != ADMXRC2_SUCCESS) {
printf("Error: failed to write SSRAM\n");
failed = TRUE;
}
status = writeSSRAM(rambuf, 4 * bankSize, bankSize, dma);
if (status != ADMXRC2_SUCCESS) {
printf("Error: failed to write SSRAM\n");
failed = TRUE;
}
fpgaSpace[6] = os_cpu_to_le32(1);
fpgaSpace[6];
while(fpgaSpace[7]!=os_cpu_to_le32(0x31));
fpgaSpace[6] = os_cpu_to_le32(0);
fpgaSpace[6];
}
for (j = 0; j < numBank; j++) {
for (k = 0; k < bankSize; k++) {
unsigned long idx = j * bankSize + k;
chkbuf[idx] = 0;
}
}
status = readSSRAM(chkbuf, 4 * bankSize, bankSize, dma);
if (status != ADMXRC2_SUCCESS) {
printf("Error: failed to read SSRAM\n");
failed = TRUE;
}
status = readSSRAM(chkbuf, 3 * bankSize, bankSize, dma);
if (status != ADMXRC2_SUCCESS) {
printf("Error: failed to read SSRAM\n");
failed = TRUE;
}
for (j = 0;j < 50;j++){
printf("\n%02d %08X %08X ", j,chkbuf[j+3*bankSize],chkbuf[4*bankSize+j]);
}
if (!failed && nError == 0) {
printf("PASSED\n");
} else {
printf("*** FAILED with %ld error(s)\n", (long) nError);
break;
}
}
if (failed) {
break;
}
}
if (speed) {
/*
** Measure the host read and host write speeds of the SSRAM,
** using DMA.
*/
float bytes, rate;
double delta;
struct timeval start, now, elapsed;
printf("Measuring access speed...\n");
start = get_time();
bytes = 0.0f;
do {
readSSRAM(rambuf, 0, memorySize, dma);
bytes += (float) (memorySize * sizeof(uint32_t));
now = get_time();
elapsed = time_subtract(&now, &start);
delta = time_to_double(&elapsed);
} while (delta < 2.0);
rate = bytes / delta;
printf("SSRAM to host throughput = %.1fMB/s\n", rate / 1048576.0f);
start = get_time();
bytes = 0.0f;
do {
writeSSRAM(rambuf, 0, memorySize, dma);
bytes += (float) (memorySize * sizeof(uint32_t));
now = get_time();
elapsed = time_subtract(&now, &start);
delta = time_to_double(&elapsed);
} while (delta < 2.0);
rate = bytes / delta;
printf("Host to SSRAM throughput = %.1fMB/s\n", rate / 1048576.0f);
}
done:
if (rambuf != NULL) {
ADMXRC2_Free(rambuf);
}
if (chkbuf != NULL) {
ADMXRC2_Free(chkbuf);
}
if (dmaDesc1Valid) {
ADMXRC2_UnsetupDMA(card, dmaDesc1);
}
if (dmaDesc2Valid) {
ADMXRC2_UnsetupDMA(card, dmaDesc2);
}
if (card != ADMXRC2_HANDLE_INVALID_VALUE) {
ADMXRC2_CloseCard(card);
}
return ret;
}
int card_initialize( void ){
const float mclk_freq = 33.0f;
ADMXRC2_STATUS status;
ADMXRC2_CARD_INFO cardInfo;
ADMXRC2_SPACE_INFO spInfo;
ADMXRC2_BANK_INFO bankInfo, bankInfo2;
const char* filename;
unsigned long i;
uint32_t sizeReg;
BOOLEAN use64bit = FALSE;
ADMXRC2_CARDID cardID = 0;
status = ADMXRC2_OpenCard(cardID, &card);
if (status != ADMXRC2_SUCCESS) {
printf("*** Failed to open card with ID %ld: %s\n",
(unsigned long) cardID, ADMXRC2_GetStatusString(status));
if (card != ADMXRC2_HANDLE_INVALID_VALUE) {
ADMXRC2_CloseCard(card);
}
return -1;
}
/*
** Get card information, specifically for device fitted and
** number of SSRAM banks
*/
status = ADMXRC2_GetCardInfo(card, &cardInfo);
if (status != ADMXRC2_SUCCESS) {
printf("*** Failed to get card info: %s\n", ADMXRC2_GetStatusString(status));
return -1;
}
/*
** Check that the type, size, width etc. of each SSRAM bank
** is the same.
*/
status = ADMXRC2_GetBankInfo(card, i, &bankInfo2);
if (status != ADMXRC2_SUCCESS) {
printf("*** Failed to get bank %ld info: %s\n",
(unsigned long) i,
ADMXRC2_GetStatusString(status));
return -1;
}
memcpy(&bankInfo, &bankInfo2, sizeof(bankInfo));
bankSize = (bankInfo.Width / 8) * bankInfo.Size / 4;
/*
** Calculate memory size in longwords (32-bit words)
*/
numBank = cardInfo.NumRAMBank;
memorySize = numBank * bankSize;
lastPageSize = memorySize & (pageSize - 1);
/*
** Determine value to program into the SIZE register in the FPGA
*/
switch (bankInfo.Size) {
case 128*1024:
sizeReg = 0;
break;
case 256*1024:
sizeReg = 1;
break;
case 512*1024:
sizeReg = 2;
break;
case 1024*1024:
sizeReg = 3;
break;
default:
printf("*** SSRAM of %ld words x %ld is not supported by this application\n",
(unsigned long) bankInfo.Size, (unsigned long) bankInfo.Width);
if (card != ADMXRC2_HANDLE_INVALID_VALUE) {
ADMXRC2_CloseCard(card);
}
return -1;
}
status = ADMXRC2_SetClockRate(card, ADMXRC2_CLOCK_LCLK, 33.0e6, NULL);
if (status != ADMXRC2_SUCCESS) {
printf("*** Failed to set LCLK to %.1fMHz: %s\n",
33.0e6, ADMXRC2_GetStatusString(status));
if (card != ADMXRC2_HANDLE_INVALID_VALUE) {
ADMXRC2_CloseCard(card);
}
return -1;
}
// ssram = (volatile uint32_t*) (((uint8_t*) fpgaSpace) + ssramOffset);
rambuf = (uint32_t*) ADMXRC2_Malloc(memorySize * sizeof(uint32_t));
if (rambuf == NULL) {
printf("*** Failed to allocate RAM buffer - aborting\n");
if (card != ADMXRC2_HANDLE_INVALID_VALUE) {
ADMXRC2_CloseCard(card);
}
return -1;
}
chkbuf = (uint32_t*) ADMXRC2_Malloc(memorySize * sizeof(uint32_t));
if (chkbuf == NULL) {
printf("*** Failed to allocate RAM readback buffer - aborting\n");
if (card != ADMXRC2_HANDLE_INVALID_VALUE) {
ADMXRC2_CloseCard(card);
}
return -1;
}
if (cardInfo.BoardType != ADMXRC2_BOARD_ADMXRC2_PRO_LITE) {
status = ADMXRC2_SetClockRate(card, 1, mclk_freq * 1.0e6, NULL);
if (status != ADMXRC2_SUCCESS) {
printf("*** Failed to set clock 1 to %.1fMHz: %s\n",
mclk_freq, ADMXRC2_GetStatusString(status));
return -1;
}
}
/*
if (use64bit) {
uint32_t config;
config = ADMXRC2_SPACE_SET_WIDTH | ADMXRC2_SPACE_WIDTH_64;
status = ADMXRC2_SetSpaceConfig(card, 0, config);
if (status != ADMXRC2_SUCCESS) {
printf ("*** Failed to set space configuration: %s\n",
ADMXRC2_GetStatusString(status));
return -1;
}
}
*/
//*************************************DMA DESCRIPTORS**************************************
status = ADMXRC2_SetupDMA(card,
rambuf,
memorySize * sizeof(uint32_t),
0,
&dmaDesc1);
if (status != ADMXRC2_SUCCESS) {
printf ("*** Failed to get a DMA descriptor: %s\n",
ADMXRC2_GetStatusString(status));
return -1;
}
status = ADMXRC2_SetupDMA(card,
chkbuf,
memorySize * sizeof(uint32_t),
0,
&dmaDesc2);
if (status != ADMXRC2_SUCCESS) {
printf ("*** Failed to get a DMA descriptor: %s\n",
ADMXRC2_GetStatusString(status));
return -1;
}
/* Get the address of FPGA space */
status = ADMXRC2_GetSpaceInfo(card, 0, &spInfo);
if (status != ADMXRC2_SUCCESS) {
printf("Failed to get space 0 info: %s\n",
ADMXRC2_GetStatusString(status));
return -1;
}
fpgaSpace = (volatile uint32_t*) spInfo.VirtualBase;
//*********************************************************************************************
dmaMode = ADMXRC2_BuildDMAModeWord(cardInfo.BoardType,
use64bit ? ADMXRC2_IOWIDTH_64 : ADMXRC2_IOWIDTH_32,
0,
ADMXRC2_DMAMODE_USEREADY | ADMXRC2_DMAMODE_USEBTERM | ADMXRC2_DMAMODE_BURSTENABLE);
/* Wait for DLLs/DCMs to lock */
sleep(1);
fpgaSpace[ZBT_SIZE_REG] = sizeReg;
fpgaSpace[ZBT_SIZE_REG]; /* make sure it's got there */
//Set the FPGA to pipelined mode
fpgaSpace[ZBT_PIPELINE_REG] = 0x1;
fpgaSpace[ZBT_PIPELINE_REG]; /* make sure it's got there */
return 0;
}
int fpga_init(char *bitfilename, float freq) {
ADMXRC2_STATUS status;
ADMXRC2_CARD_INFO cardInfo;
ADMXRC2_SPACE_INFO spInfo;
volatile void* fpgaSpace;
uint32_t regval;
double tmpd;
/* Open accelerator card. */
status = ADMXRC2_OpenCard(cardID, &card);
if (status != ADMXRC2_SUCCESS) {
printf("Failed to open card with ID %ld: %s\n",
(unsigned long) cardID, ADMXRC2_GetStatusString(status));
return -1;
}
/* Check validity of card */
status = ADMXRC2_GetCardInfo(card, &cardInfo);
if (status != ADMXRC2_SUCCESS) {
printf("Failed to get card info: %s\n", ADMXRC2_GetStatusString(status));
return -1;
}
if (cardInfo.BoardType != ADMXRC2_BOARD_ADMXRC5T2) {
printf("Cannot find a ADM-XRC-5T2 card.\n");
return -1;
}
/* Get the address of FPGA space */
status = ADMXRC2_GetSpaceInfo(card, 0, &spInfo);
if (status != ADMXRC2_SUCCESS) {
printf("Failed to get space 0 info: %s\n",
ADMXRC2_GetStatusString(status));
return -1;
}
fpgaSpace = spInfo.VirtualBase;
if (fpgaSpace == NULL) {
printf("Failed to get valid space pointer.\n");
return -1;
}
fpgaReg = (volatile uint32_t *)fpgaSpace;
fpgaMem = (volatile uint8_t *)fpgaSpace + WINDOW_SIZE;
/* Set local bus clock to nominal frequency */
status = ADMXRC2_SetClockRate(card, ADMXRC2_CLOCK_LCLK, LCLK_FREQ*1e6, &tmpd);
if (status != ADMXRC2_SUCCESS) {
printf("Failed to set LCLK to %.1fMHz: %s\n",
LCLK_FREQ, ADMXRC2_GetStatusString(status));
return -1;
}
#ifdef __DEBUG__
printf("LCLK = %lfMHz\n", tmpd/1000000);
#endif
/* Set memory clock to nominal frequency */
status = ADMXRC2_SetClockRate(card, 1, freq*1e6, &tmpd);
if (status != ADMXRC2_SUCCESS) {
printf("Failed to set LCLK to %.1fMHz: %s\n",
MCLK_FREQ, ADMXRC2_GetStatusString(status));
return -1;
}
#ifdef __DEBUG__
printf("MCLK = %lfMHz\n", tmpd/1000000);
#endif
/* Configure FPGA device using the bit file. */
status = ADMXRC2_ConfigureFromFile(card, bitfilename);
if (status != ADMXRC2_SUCCESS) {
printf ("Failed to load the bitstream '%s': %s\n",
bitfilename, ADMXRC2_GetStatusString(status));
return -1;
}
/* Wait until LCLK locked. */
sleep_ms(500);
regval = fpgaReg[STATUS_REG];
if (!(regval & STATUS_REG_LCLKLOCKED)) {
printf("*** LCLK DCM not locked: status = 0x%08x\n", regval);
return -1;
}
#ifdef __DEBUG__
printf("STATUS_REG = %08X\n", regval);
#endif
/* Clear old sticky unlock value */
fpgaReg[STATUS_REG] = STATUS_REG_LCLKSTICKY;
fpgaReg[STATUS_REG];
/* Set card in 64-bit mode */
status = ADMXRC2_SetSpaceConfig(card, 0,
ADMXRC2_SPACE_SET_WIDTH | ADMXRC2_SPACE_WIDTH_64);
if (status != ADMXRC2_SUCCESS) {
printf ("*** Failed to set space configuration: %s\n",
ADMXRC2_GetStatusString(status));
return -1;
}
dmaModeWord = ADMXRC2_BuildDMAModeWord(ADMXRC2_BOARD_ADMXRC5T2,
ADMXRC2_IOWIDTH_64, 0, DMA_MODE);
/* Set correct mode to memory ports */
fpgaReg[MODEx_REG(0)] = SDRAM_MODE;
fpgaReg[MODEx_REG(1)] = SDRAM_MODE;
fpgaReg[MODEx_REG(2)] = SDRAM_MODE;
fpgaReg[MODEx_REG(3)] = SDRAM_MODE;
fpgaReg[MODEx_REG(4)] = SSRAM_MODE;
fpgaReg[MODEx_REG(5)] = SSRAM_MODE;
/* Reset Memory subsystem */
fpgaReg[MEMCTL_REG] = 1;
fpgaReg[MEMCTL_REG];
sleep_ms(1);
fpgaReg[MEMCTL_REG] = 0;
fpgaReg[MEMCTL_REG];
sleep_ms(500);
/* Check MCLK DCM locked and memory ready */
regval = fpgaReg[STATUS_REG];
if ((regval & MCLK_MASK) != MCLK_MASK) {
printf("*** MCLK DCM not locked: status = 0x%08x\n", regval);
return -1;
}
#ifdef __DEBUG__
printf("STATUS_REG = %08X\n", regval);
#endif
regval = 0xffU << STATUS_REG_SHIFT_STICKY;
fpgaReg[STATUS_REG] = regval;
fpgaReg[STATUS_REG];
regval = fpgaReg[MEMSTAT_REG];
if ((regval & MEMSTAT_MASK) != MEMSTAT_MASK) {
printf("*** Memory not ready: status = 0x%08x\n", regval);
return -1;
}
#ifdef __DEBUG__
printf("MEMSTAT_REG = %08X\n", regval);
#endif
return 0;
}