/* Expects AFU struct to have recently been zeroed out */
static int cxl_read_afu_descriptor(struct cxl_afu *afu)
{
u64 val;
val = AFUD_READ_INFO(afu);
afu->pp_irqs = AFUD_NUM_INTS_PER_PROC(val);
afu->max_procs_virtualised = AFUD_NUM_PROCS(val);
afu->crs_num = AFUD_NUM_CRS(val);
if (AFUD_AFU_DIRECTED(val))
afu->modes_supported |= CXL_MODE_DIRECTED;
if (AFUD_DEDICATED_PROCESS(val))
afu->modes_supported |= CXL_MODE_DEDICATED;
if (AFUD_TIME_SLICED(val))
afu->modes_supported |= CXL_MODE_TIME_SLICED;
val = AFUD_READ_PPPSA(afu);
afu->pp_size = AFUD_PPPSA_LEN(val) * 4096;
afu->psa = AFUD_PPPSA_PSA(val);
if ((afu->pp_psa = AFUD_PPPSA_PP(val)))
afu->pp_offset = AFUD_READ_PPPSA_OFF(afu);
val = AFUD_READ_CR(afu);
afu->crs_len = AFUD_CR_LEN(val) * 256;
afu->crs_offset = AFUD_READ_CR_OFF(afu);
return 0;
}
static void dump_afu_descriptor(struct cxl_afu *afu)
{
u64 val, afu_cr_num, afu_cr_off, afu_cr_len;
int i;
#define show_reg(name, what) \
dev_info(&afu->dev, "afu desc: %30s: %#llx\n", name, what)
val = AFUD_READ_INFO(afu);
show_reg("num_ints_per_process", AFUD_NUM_INTS_PER_PROC(val));
show_reg("num_of_processes", AFUD_NUM_PROCS(val));
show_reg("num_of_afu_CRs", AFUD_NUM_CRS(val));
show_reg("req_prog_mode", val & 0xffffULL);
afu_cr_num = AFUD_NUM_CRS(val);
val = AFUD_READ(afu, 0x8);
show_reg("Reserved", val);
val = AFUD_READ(afu, 0x10);
show_reg("Reserved", val);
val = AFUD_READ(afu, 0x18);
show_reg("Reserved", val);
val = AFUD_READ_CR(afu);
show_reg("Reserved", (val >> (63-7)) & 0xff);
show_reg("AFU_CR_len", AFUD_CR_LEN(val));
afu_cr_len = AFUD_CR_LEN(val) * 256;
val = AFUD_READ_CR_OFF(afu);
afu_cr_off = val;
show_reg("AFU_CR_offset", val);
val = AFUD_READ_PPPSA(afu);
show_reg("PerProcessPSA_control", (val >> (63-7)) & 0xff);
show_reg("PerProcessPSA Length", AFUD_PPPSA_LEN(val));
val = AFUD_READ_PPPSA_OFF(afu);
show_reg("PerProcessPSA_offset", val);
val = AFUD_READ_EB(afu);
show_reg("Reserved", (val >> (63-7)) & 0xff);
show_reg("AFU_EB_len", AFUD_EB_LEN(val));
val = AFUD_READ_EB_OFF(afu);
show_reg("AFU_EB_offset", val);
for (i = 0; i < afu_cr_num; i++) {
val = AFUD_READ_LE(afu, afu_cr_off + i * afu_cr_len);
show_reg("CR Vendor", val & 0xffff);
show_reg("CR Device", (val >> 16) & 0xffff);
}
#undef show_reg
}
/* Expects AFU struct to have recently been zeroed out */
static int cxl_read_afu_descriptor(struct cxl_afu *afu)
{
u64 val;
val = AFUD_READ_INFO(afu);
afu->pp_irqs = AFUD_NUM_INTS_PER_PROC(val);
afu->max_procs_virtualised = AFUD_NUM_PROCS(val);
afu->crs_num = AFUD_NUM_CRS(val);
if (AFUD_AFU_DIRECTED(val))
afu->modes_supported |= CXL_MODE_DIRECTED;
if (AFUD_DEDICATED_PROCESS(val))
afu->modes_supported |= CXL_MODE_DEDICATED;
if (AFUD_TIME_SLICED(val))
afu->modes_supported |= CXL_MODE_TIME_SLICED;
val = AFUD_READ_PPPSA(afu);
afu->pp_size = AFUD_PPPSA_LEN(val) * 4096;
afu->psa = AFUD_PPPSA_PSA(val);
if ((afu->pp_psa = AFUD_PPPSA_PP(val)))
afu->pp_offset = AFUD_READ_PPPSA_OFF(afu);
val = AFUD_READ_CR(afu);
afu->crs_len = AFUD_CR_LEN(val) * 256;
afu->crs_offset = AFUD_READ_CR_OFF(afu);
/* eb_len is in multiple of 4K */
afu->eb_len = AFUD_EB_LEN(AFUD_READ_EB(afu)) * 4096;
afu->eb_offset = AFUD_READ_EB_OFF(afu);
/* eb_off is 4K aligned so lower 12 bits are always zero */
if (EXTRACT_PPC_BITS(afu->eb_offset, 0, 11) != 0) {
dev_warn(&afu->dev,
"Invalid AFU error buffer offset %Lx\n",
afu->eb_offset);
dev_info(&afu->dev,
"Ignoring AFU error buffer in the descriptor\n");
/* indicate that no afu buffer exists */
afu->eb_len = 0;
}
return 0;
}
static void dump_afu_descriptor(struct cxl_afu *afu)
{
u64 val;
#define show_reg(name, what) \
dev_info(&afu->dev, "afu desc: %30s: %#llx\n", name, what)
val = AFUD_READ_INFO(afu);
show_reg("num_ints_per_process", AFUD_NUM_INTS_PER_PROC(val));
show_reg("num_of_processes", AFUD_NUM_PROCS(val));
show_reg("num_of_afu_CRs", AFUD_NUM_CRS(val));
show_reg("req_prog_mode", val & 0xffffULL);
val = AFUD_READ(afu, 0x8);
show_reg("Reserved", val);
val = AFUD_READ(afu, 0x10);
show_reg("Reserved", val);
val = AFUD_READ(afu, 0x18);
show_reg("Reserved", val);
val = AFUD_READ_CR(afu);
show_reg("Reserved", (val >> (63-7)) & 0xff);
show_reg("AFU_CR_len", AFUD_CR_LEN(val));
val = AFUD_READ_CR_OFF(afu);
show_reg("AFU_CR_offset", val);
val = AFUD_READ_PPPSA(afu);
show_reg("PerProcessPSA_control", (val >> (63-7)) & 0xff);
show_reg("PerProcessPSA Length", AFUD_PPPSA_LEN(val));
val = AFUD_READ_PPPSA_OFF(afu);
show_reg("PerProcessPSA_offset", val);
val = AFUD_READ_EB(afu);
show_reg("Reserved", (val >> (63-7)) & 0xff);
show_reg("AFU_EB_len", AFUD_EB_LEN(val));
val = AFUD_READ_EB_OFF(afu);
show_reg("AFU_EB_offset", val);
#undef show_reg
}