t_stat clk_svc (UNIT *uptr) { int32 t; if (clk_csr & CSR_IE) SET_INT (CLK); t = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */ sim_activate_after (uptr, 1000000/clk_tps); /* reactivate unit */ tmr_poll = t; /* set tmr poll */ tmxr_poll = t * TMXR_MULT; /* set mux poll */ AIO_SET_INTERRUPT_LATENCY(tmr_poll*clk_tps); /* set interrrupt latency */ return SCPE_OK; }
t_stat clk_svc (UNIT *uptr) { int32 t; if (clk_csr & CSR_IE) SET_INT (CLK); t = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */ sim_activate_after (&clk_unit, 1000000/clk_tps); /* reactivate unit */ tmr_poll = t; /* set tmr poll */ tmxr_poll = t * TMXR_MULT; /* set mux poll */ if (!todr_blow && todr_reg) /* if running? */ todr_reg = todr_reg + 1; /* incr TODR */ AIO_SET_INTERRUPT_LATENCY(tmr_poll*clk_tps); /* set interrrupt latency */ return SCPE_OK; }
t_stat tmr_svc (UNIT *uptr) { sim_debug (TMR_DB_TICK, &tmr_dev, "tmr_svc()\n"); tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */ if (tmr_iccs & TMR_CSR_DON) /* done? set err */ tmr_iccs = tmr_iccs | TMR_CSR_ERR; else tmr_iccs = tmr_iccs | TMR_CSR_DON; /* set done */ if (tmr_iccs & TMR_CSR_RUN) /* run? */ tmr_sched (tmr_nicr); /* reactivate */ if (tmr_iccs & TMR_CSR_IE) { /* ie? set int req */ tmr_int = 1; sim_debug (TMR_DB_INT, &tmr_dev, "tmr_svc() - INT=1\n"); } else tmr_int = 0; AIO_SET_INTERRUPT_LATENCY(tmr_poll*clk_tps); /* set interrrupt latency */ return SCPE_OK; }