//*****************************************************************************
//
//! @brief Starts the watchdog timer.
//!
//! Enables the watchdog timer tick using the 'enable' bit in the watchdog
//! configuration register. This function does not perform any locking of the
//! watchdog timer, so it can be disabled or reconfigured later.
//!
//! @return None.
//
//*****************************************************************************
void
am_hal_wdt_start(void)
{
//
// Make sure the watchdog timer is in the "reset" state, and then set the
// enable bit to start counting.
//
AM_REGn(WDT, 0, CFG) |= AM_REG_WDT_CFG_WDTEN_M;
AM_REGn(WDT, 0, RSTRT) |= AM_REG_WDT_RSTRT_RSTRT_KEYVALUE;
}
static void
apollo2_uart_irqh_x(int num)
{
struct apollo2_uart *u;
uint32_t status;
int data;
int rc;
os_trace_enter_isr();
u = &uarts[num];
status = AM_REGn(UART, 0, IES);
AM_REGn(UART, 0, IEC) &= ~status;
if (status & (AM_REG_UART_IES_TXRIS_M)) {
if (u->u_tx_started) {
while (1) {
if (AM_BFRn(UART, 0, FR, TXFF)) {
break;
}
data = u->u_tx_func(u->u_func_arg);
if (data < 0) {
if (u->u_tx_done) {
u->u_tx_done(u->u_func_arg);
}
apollo2_uart_disable_tx_irq();
u->u_tx_started = 0;
break;
}
AM_REGn(UART, 0, DR) = data;
}
}
}
if (status & (AM_REG_UART_IES_RXRIS_M | AM_REG_UART_IES_RTRIS_M)) {
/* Service receive buffer */
while (!AM_BFRn(UART, 0, FR, RXFE)) {
u->u_rx_buf = AM_REGn(UART, 0, DR);
rc = u->u_rx_func(u->u_func_arg, u->u_rx_buf);
if (rc < 0) {
u->u_rx_stall = 1;
break;
}
}
}
os_trace_exit_isr();
}
//*****************************************************************************
//
//! @brief Returns either the enabled or raw stimer interrupt status.
//!
//! This function will return the stimer interrupt status.
//!
//! @bEnabledOnly if true returns the status of the enabled interrupts
//! only.
//!
//! The return value will be the logical OR of one or more of the following
//! values:
//!
//!
//! @return Returns the stimer interrupt status.
//
//*****************************************************************************
uint32_t
am_hal_stimer_int_status_get(bool bEnabledOnly)
{
//
// Return the desired status.
//
uint32_t ui32RetVal = AM_REGn(CTIMER, 0, STMINTSTAT);
if ( bEnabledOnly )
{
ui32RetVal &= AM_REGn(CTIMER, 0, STMINTEN);
}
return ui32RetVal;
}
//*****************************************************************************
//
//! @brief Locks the watchdog configuration and starts the watchdog timer.
//!
//! This function sets the watchdog "lock" register, which prevents software
//! from re-configuring the watchdog. This action will also set the enable bit
//! for the watchdog timer, so it will start counting immediately.
//!
//! @return None.
//
//*****************************************************************************
void
am_hal_wdt_lock_and_start(void)
{
//
// Write the 'key' value to the watchdog lock register.
//
AM_REGn(WDT, 0, LOCK) = AM_REG_WDT_LOCK_LOCK_KEYVALUE;
}
//*****************************************************************************
//
//! @brief Clears the selected stimer interrupt.
//!
//! @param ui32Interrupt is the interrupt to be used.
//!
//! This function will clear the selected interrupts in the STIMER
//! interrupt register.
//!
//! ui32Interrupt should be the logical OR of one or more of the following
//! values:
//!
//! AM_HAL_STIMER_INT_COMPAREA
//! AM_HAL_STIMER_INT_COMPAREB
//! AM_HAL_STIMER_INT_COMPAREC
//! AM_HAL_STIMER_INT_COMPARED
//! AM_HAL_STIMER_INT_COMPAREE
//! AM_HAL_STIMER_INT_COMPAREF
//! AM_HAL_STIMER_INT_COMPAREG
//! AM_HAL_STIMER_INT_COMPAREH
//!
//! AM_HAL_STIMER_INT_OVERFLOW
//!
//! AM_HAL_STIMER_INT_CAPTUREA
//! AM_HAL_STIMER_INT_CAPTUREB
//! AM_HAL_STIMER_INT_CAPTUREC
//! AM_HAL_STIMER_INT_CAPTURED
//!
//! @return None.
//
//*****************************************************************************
void
am_hal_stimer_int_clear(uint32_t ui32Interrupt)
{
//
// Disable the interrupt at the module level.
//
AM_REGn(CTIMER, 0, STMINTCLR) = ui32Interrupt;
}
//*****************************************************************************
//
//! @brief Sets the selected stimer interrupt.
//!
//! @param ui32Interrupt is the interrupt to be used.
//!
//! This function will set the selected interrupts in the STIMER
//! interrupt register.
//!
//! ui32Interrupt should be the logical OR of one or more of the following
//! values:
//!
//! AM_HAL_STIMER_INT_COMPAREA
//! AM_HAL_STIMER_INT_COMPAREB
//! AM_HAL_STIMER_INT_COMPAREC
//! AM_HAL_STIMER_INT_COMPARED
//! AM_HAL_STIMER_INT_COMPAREE
//! AM_HAL_STIMER_INT_COMPAREF
//! AM_HAL_STIMER_INT_COMPAREG
//! AM_HAL_STIMER_INT_COMPAREH
//!
//! AM_HAL_STIMER_INT_OVERFLOW
//!
//! AM_HAL_STIMER_INT_CAPTUREA
//! AM_HAL_STIMER_INT_CAPTUREB
//! AM_HAL_STIMER_INT_CAPTUREC
//! AM_HAL_STIMER_INT_CAPTURED
//!
//! @return None.
//
//*****************************************************************************
void
am_hal_stimer_int_set(uint32_t ui32Interrupt)
{
//
// Set the interrupts.
//
AM_REGn(CTIMER, 0, STMINTSET) = ui32Interrupt;
}
//*****************************************************************************
//
//! @brief Disables the selected stimer interrupt.
//!
//! @param ui32Interrupt is the interrupt to be used.
//!
//! This function will disable the selected interrupts in the STIMER
//! interrupt register.
//!
//! ui32Interrupt should be the logical OR of one or more of the following
//! values:
//!
//! AM_HAL_STIMER_INT_COMPAREA
//! AM_HAL_STIMER_INT_COMPAREB
//! AM_HAL_STIMER_INT_COMPAREC
//! AM_HAL_STIMER_INT_COMPARED
//! AM_HAL_STIMER_INT_COMPAREE
//! AM_HAL_STIMER_INT_COMPAREF
//! AM_HAL_STIMER_INT_COMPAREG
//! AM_HAL_STIMER_INT_COMPAREH
//!
//! AM_HAL_STIMER_INT_OVERFLOW
//!
//! AM_HAL_STIMER_INT_CAPTUREA
//! AM_HAL_STIMER_INT_CAPTUREB
//! AM_HAL_STIMER_INT_CAPTUREC
//! AM_HAL_STIMER_INT_CAPTURED
//!
//! @return None.
//
//*****************************************************************************
void
am_hal_stimer_int_disable(uint32_t ui32Interrupt)
{
//
// Disable the interrupt at the module level.
//
AM_REGn(CTIMER, 0, STMINTEN) &= ~ui32Interrupt;
}
//*****************************************************************************
//
//! @brief Return the enabled stimer interrupts.
//!
//! This function will return all enabled interrupts in the STIMER
//! interrupt enable register.
//!
//! @return return enabled interrupts. This will be a logical or of:
//!
//! AM_HAL_STIMER_INT_COMPAREA
//! AM_HAL_STIMER_INT_COMPAREB
//! AM_HAL_STIMER_INT_COMPAREC
//! AM_HAL_STIMER_INT_COMPARED
//! AM_HAL_STIMER_INT_COMPAREE
//! AM_HAL_STIMER_INT_COMPAREF
//! AM_HAL_STIMER_INT_COMPAREG
//! AM_HAL_STIMER_INT_COMPAREH
//!
//! AM_HAL_STIMER_INT_OVERFLOW
//!
//! AM_HAL_STIMER_INT_CAPTUREA
//! AM_HAL_STIMER_INT_CAPTUREB
//! AM_HAL_STIMER_INT_CAPTUREC
//! AM_HAL_STIMER_INT_CAPTURED
//!
//! @return Return the enabled timer interrupts.
//
//*****************************************************************************
uint32_t
am_hal_stimer_int_enable_get(void)
{
//
// Return enabled interrupts.
//
return AM_REGn(CTIMER, 0, STMINTEN);
}
//*****************************************************************************
//
//! @brief Stops the watchdog timer.
//!
//! Disables the watchdog timer tick by clearing the 'enable' bit in the
//! watchdog configuration register.
//!
//! @return None.
//
//*****************************************************************************
void
am_hal_wdt_halt(void)
{
//
// Clear the watchdog enable bit.
//
AM_REGn(WDT, 0, CFG) &= ~AM_REG_WDT_CFG_WDTEN_M;
}
void
hal_uart_blocking_tx(int port, uint8_t data)
{
struct apollo2_uart *u;
if (port >= UART_CNT) {
return;
}
u = &uarts[port];
if (!u->u_open) {
return;
}
while (AM_BFRn(UART, 0, FR, TXFF));
AM_REGn(UART, 0, DR) = data;
}
void
hal_uart_start_tx(int port)
{
struct apollo2_uart *u;
os_sr_t sr;
int data;
if (port >= UART_CNT) {
return;
}
u = &uarts[port];
if (!u->u_open) {
return;
}
OS_ENTER_CRITICAL(sr);
if (u->u_tx_started == 0) {
while (1) {
if (AM_BFRn(UART, 0, FR, TXFF)) {
u->u_tx_started = 1;
apollo2_uart_enable_tx_irq();
break;
}
data = u->u_tx_func(u->u_func_arg);
if (data < 0) {
if (u->u_tx_done) {
u->u_tx_done(u->u_func_arg);
}
break;
}
AM_REGn(UART, 0, DR) = data;
}
}
OS_EXIT_CRITICAL(sr);
}
//*****************************************************************************
//
//! @brief Configure the watchdog timer.
//!
//! @param psConfig - pointer to a configuration structure containing the
//! desired watchdog settings.
//!
//! This function will set the watchdog configuration register based on the
//! user's desired settings listed in the structure referenced by psConfig. If
//! the structure indicates that watchdog interrupts are desired, this function
//! will also set the interrupt enable bit in the configuration register.
//!
//! @note In order to actually receive watchdog interrupt and/or watchdog reset
//! events, the caller will also need to make sure that the watchdog interrupt
//! vector is enabled in the ARM NVIC, and that watchdog resets are enabled in
//! the reset generator module. Otherwise, the watchdog-generated interrupt and
//! reset events will have no effect.
//!
//! @return None.
//
//*****************************************************************************
void
am_hal_wdt_init(const am_hal_wdt_config_t *psConfig)
{
uint32_t ui32ConfigVal;
uint16_t ui16IntCount, ui16ResetCount;
bool bResetEnabled = psConfig->ui32Config & AM_HAL_WDT_ENABLE_RESET;
bool bInterruptEnabled = psConfig->ui32Config & AM_HAL_WDT_ENABLE_INTERRUPT;
//
// Read the desired settings from the psConfig structure.
//
ui16IntCount = psConfig->ui16InterruptCount;
ui16ResetCount = psConfig->ui16ResetCount;
//
// Write the interrupt and reset count values to a temporary variable.
//
// Accept the passed Config value, but clear the Counts that we are about to set.
ui32ConfigVal = psConfig->ui32Config & ~(AM_REG_WDT_CFG_INTVAL_M | AM_REG_WDT_CFG_RESVAL_M);
ui32ConfigVal |= AM_WRITE_SM(AM_REG_WDT_CFG_INTVAL, ui16IntCount);
ui32ConfigVal |= AM_WRITE_SM(AM_REG_WDT_CFG_RESVAL, ui16ResetCount);
//
// If interrupts should be enabled, set the appropriate bit in the
// temporary variable. Also, enable the interrupt in INTEN register in the
// watchdog module.
//
if ( bInterruptEnabled )
{
//
// Enable the watchdog interrupt if the configuration calls for them.
//
AM_REGn(WDT, 0, INTEN) |= AM_REG_WDT_INTEN_WDT_M;
}
else
{
//
// Disable the watchdog interrupt if the configuration doesn't call for
// watchdog interrupts.
//
AM_REGn(WDT, 0, INTEN) &= ~AM_REG_WDT_INTEN_WDT_M;
}
//
// If resets should be enabled, set the appropriate bit in the temporary
// variable.
//
if ( bResetEnabled )
{
//
// Also enable watchdog resets in the reset module.
//
AM_REG(RSTGEN, CFG) |= AM_REG_RSTGEN_CFG_WDREN_M;
}
else
{
//
// Disable watchdog resets in the reset module.
//
AM_REG(RSTGEN, CFG) &= ~AM_REG_RSTGEN_CFG_WDREN_M;
}
//
// Check for a user specified clock select. If none specified then
// set 128Hz.
//
if ( !(psConfig->ui32Config & AM_REG_WDT_CFG_CLKSEL_M) )
{
ui32ConfigVal |= AM_REG_WDT_CFG_CLKSEL_128HZ;
}
//
// Write the saved value to the watchdog configuration register.
//
AM_REGn(WDT, 0, CFG) = ui32ConfigVal;
}
//*****************************************************************************
//
//! @brief Clear the state of the wdt interrupt status bit.
//!
//! This function clear the interrupt bit.
//!
//! @return None
//
//*****************************************************************************
void
am_hal_wdt_int_clear(void)
{
AM_REGn(WDT, 0, INTCLR) = AM_REG_WDT_INTCLR_WDT_M;
}
static inline void
apollo2_uart_disable_rx_irq(void)
{
AM_REGn(UART, 0, IER) &= ~(AM_REG_UART_IER_RTIM_M |
AM_REG_UART_IER_RXIM_M);
}
static inline void
apollo2_uart_enable_tx_irq(void)
{
AM_REGn(UART, 0, IER) |= (AM_REG_UART_IER_TXIM_M);
}
