static void ar9002_hw_fill_txdesc(struct ath_hw *ah, void *ds, u32 seglen,
bool is_firstseg, bool is_lastseg,
const void *ds0, dma_addr_t buf_addr,
unsigned int qcu)
{
struct ar5416_desc *ads = AR5416DESC(ds);
ads->ds_data = buf_addr;
if (is_firstseg) {
ads->ds_ctl1 |= seglen | (is_lastseg ? 0 : AR_TxMore);
} else if (is_lastseg) {
ads->ds_ctl0 = 0;
ads->ds_ctl1 = seglen;
ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
} else {
ads->ds_ctl0 = 0;
ads->ds_ctl1 = seglen | AR_TxMore;
ads->ds_ctl2 = 0;
ads->ds_ctl3 = 0;
}
ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
}
HAL_BOOL ar5416FillTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds,
a_uint32_t segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
const struct ath_tx_desc *ds0)
{
struct ar5416_desc *ads = AR5416DESC(ds);
// a_uint32_t offset = 70;
// char *data_ptr = ds->ds_data;
// data_ptr[offset+0] = 'w';
// data_ptr[offset+1] = 'e';
// data_ptr[offset+2] = 'a';
// data_ptr[offset+3] = 'r';
// data_ptr[offset+4] = 'e';
// data_ptr[offset+5] = 'h';
// data_ptr[offset+6] = 'e';
// data_ptr[offset+7] = 'r';
// data_ptr[offset+8] = 'e';
HALASSERT((segLen &~ AR_BufLen) == 0);
if (firstSeg) {
/*
* First descriptor, don't clobber xmit control data
* setup by ar5416SetupTxDesc.
*/
ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_TxMore);
} else if (lastSeg) {
/*
* Last descriptor in a multi-descriptor frame,
* copy the multi-rate transmit parameters from
* the first frame for processing on completion.
*/
ads->ds_ctl0 = 0;
ads->ds_ctl1 = segLen;
ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
} else {
/*
* Intermediate descriptor in a multi-descriptor frame.
*/
ads->ds_ctl0 = 0;
ads->ds_ctl1 = segLen | AR_TxMore;
ads->ds_ctl2 = 0;
ads->ds_ctl3 = 0;
}
ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
return AH_TRUE;
}
HAL_BOOL
ar5416FillTxDesc(struct ath_hal *ah, void *ds, dma_addr_t *bufAddr,
u_int32_t *seg_len, u_int desc_id, u_int qcu, HAL_KEY_TYPE keyType, HAL_BOOL first_seg,
HAL_BOOL last_seg, const void *ds0)
{
struct ar5416_desc *ads = AR5416DESC(ds);
HALASSERT((seg_len[0] &~ AR_BufLen) == 0);
OS_MEMZERO(&(ads->u.tx.tx_status), sizeof(ads->u.tx.tx_status));
/* Set the buffer addresses */
ads->ds_data = bufAddr[0];
if (first_seg) {
/*
* First descriptor, don't clobber xmit control data
* setup by ar5416SetupTxDesc.
*/
ads->ds_ctl1 |= seg_len[0] | (last_seg ? 0 : AR_TxMore);
} else if (last_seg) { /* !first_seg && last_seg */
/*
* Last descriptor in a multi-descriptor frame,
* copy the multi-rate transmit parameters from
* the first frame for processing on completion.
*/
ads->ds_ctl0 = 0;
ads->ds_ctl1 = seg_len[0];
#ifdef AH_NEED_DESC_SWAP
ads->ds_ctl2 = __bswap32(AR5416DESC_CONST(ds0)->ds_ctl2);
ads->ds_ctl3 = __bswap32(AR5416DESC_CONST(ds0)->ds_ctl3);
#else
ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
#endif
} else { /* !first_seg && !last_seg */
/*
* Intermediate descriptor in a multi-descriptor frame.
*/
ads->ds_ctl0 = 0;
ads->ds_ctl1 = seg_len[0] | AR_TxMore;
ads->ds_ctl2 = 0;
ads->ds_ctl3 = 0;
}
return AH_TRUE;
}