void lpc2210_mach_init(ARMul_State *state, machine_config_t *this_mach)
{
//chy 2003-08-19, setprocessor
ARMul_SelectProcessor(state, ARM_v4_Prop);
//chy 2004-05-09, set lateabtSig
state->lateabtSig = HIGH;
this_mach->mach_io_do_cycle = lpc2210_io_do_cycle;
this_mach->mach_io_reset = lpc2210_io_reset;
this_mach->mach_io_read_byte = lpc2210_io_read_byte;
this_mach->mach_io_write_byte = lpc2210_io_write_byte;
this_mach->mach_io_read_halfword = lpc2210_io_read_halfword;
this_mach->mach_io_write_halfword = lpc2210_io_write_halfword;
this_mach->mach_io_read_word = lpc2210_io_read_word;
this_mach->mach_io_write_word = lpc2210_io_write_word;
this_mach->mach_update_int = lpc2210_update_int;
//ksh 2004-2-7
state->mach_io.instr = (ARMword *)&io.vic.IRQStatus;
//*state->io.instr = (ARMword *)&io.intsr;
//state->io->net_flags = (ARMword *)&io.net_flags;
//state->mach_io.net_int = (ARMword *)&io.net_int;
}
void
omap5912_mach_init (void *state, machine_config_t *mc)
{
#if 0
//chy 2003-08-19, setprocessor
ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop);
//chy 2004-05-09, set lateabtSig
state->lateabtSig = LOW;
state->Reg[1] = 515; /*mainstone machine id. */
#endif
((generic_arch_t *)state)->set_regval_by_id(1, 515); /*mainstone machine id. */
omap5912_io_reset ();
mc->mach_io_do_cycle = omap5912_io_do_cycle;
mc->mach_io_reset = omap5912_io_reset;
mc->mach_io_read_byte = omap5912_io_read_byte;
mc->mach_io_write_byte = omap5912_io_write_byte;
mc->mach_io_read_halfword = omap5912_io_read_halfword;
mc->mach_io_write_halfword = omap5912_io_write_halfword;
mc->mach_io_read_word = omap5912_io_read_word;
mc->mach_io_write_word = omap5912_io_write_word;
mc->mach_update_int = omap5912_update_int;
mc->mach_set_intr = omap_set_intr;
mc->mach_pending_intr = omap_pending_intr;
mc->mach_update_intr = omap_update_intr;
mc->state = (void *) state;
}
void
ep7312_mach_init (void* arch_instance, machine_config_t * this_mach)
{
extern ARMul_State * state;
state->abort_model = 2;
//chy 2003-08-19, setprocessor
ARMul_SelectProcessor (state, ARM_v4_Prop);
//chy 2004-05-09, set lateabtSig
state->lateabtSig = HIGH;
state->Reg[1] = 91; //for EP7212/EP7312 arch id
this_mach->mach_io_do_cycle = ep7312_io_do_cycle;
this_mach->mach_io_reset = ep7312_io_reset;
this_mach->mach_io_read_byte = ep7312_io_read_byte;
this_mach->mach_io_write_byte = ep7312_io_write_byte;
this_mach->mach_io_read_halfword = ep7312_io_read_halfword;
this_mach->mach_io_write_halfword = ep7312_io_write_halfword;
this_mach->mach_io_read_word = ep7312_io_read_word;
this_mach->mach_io_write_word = ep7312_io_write_word;
this_mach->mach_update_int = ep7312_update_int;
this_mach->state = (void *) state;
}
void
pxa250_mach_init (ARMul_State * state, machine_config_t * mc)
{
//chy 2003-08-19, setprocessor
ARMul_SelectProcessor (state,
ARM_XScale_Prop | ARM_v5_Prop | ARM_v5e_Prop);
//chy 2004-05-09, set lateabtSig
state->lateabtSig = LOW;
state->Reg[1] = 89; /*lubbock machine id. */
pxa250_io_reset ();
/*added by ksh for energy estimation in 2004-11-26 */
state->energy.cccr = pxa250_io.cccr;
mc->mach_io_do_cycle = pxa250_io_do_cycle;
mc->mach_io_reset = pxa250_io_reset;
mc->mach_io_read_byte = pxa250_io_read_byte;
mc->mach_io_write_byte = pxa250_io_write_byte;
mc->mach_io_read_halfword = pxa250_io_read_halfword;
mc->mach_io_write_halfword = pxa250_io_write_halfword;
mc->mach_io_read_word = pxa250_io_read_word;
mc->mach_io_write_word = pxa250_io_write_word;
mc->mach_set_intr = pxa_set_intr;
mc->mach_pending_intr = pxa_pending_intr;
mc->mach_update_intr = pxa_update_intr;
mc->state = (void *) state;
}
void
ep7312_mach_init (void *arch_instance, machine_config_t *this_mach)
{
#if 0
state->abort_model = 2;
//chy 2003-08-19, setprocessor
ARMul_SelectProcessor (state, ARM_v4_Prop);
//chy 2004-05-09, set lateabtSig
state->lateabtSig = HIGH;
state->Reg[1] = 91; //for EP7212/EP7312 arch id
#endif
((generic_arch_t *)arch_instance)->set_regval_by_id(1, 91); /* for EP7212/EP7312 arch id */
this_mach->mach_io_do_cycle = ep7312_io_do_cycle;
this_mach->mach_io_reset = ep7312_io_reset;
this_mach->mach_io_read_byte = ep7312_io_read_byte;
this_mach->mach_io_write_byte = ep7312_io_write_byte;
this_mach->mach_io_read_halfword = ep7312_io_read_halfword;
this_mach->mach_io_write_halfword = ep7312_io_write_halfword;
this_mach->mach_io_read_word = ep7312_io_read_word;
this_mach->mach_io_write_word = ep7312_io_write_word;
this_mach->mach_update_int = ep7312_update_int;
this_mach->state = (void *) arch_instance;
}
ARM_Interpreter::ARM_Interpreter() {
state = new ARMul_State;
state->m_MemoryMap = NULL;
ARMul_EmulateInit();
memset(state, 0, sizeof(ARMul_State));
ARMul_NewState(state);
state->abort_model = 0;
state->cpu = (cpu_config_t*)&arm11_cpu_info;
state->bigendSig = LOW;
ARMul_SelectProcessor(state, ARM_v6_Prop | ARM_v5_Prop | ARM_v5e_Prop);
state->lateabtSig = LOW;
// Reset the core to initial state
ARMul_CoProInit(state);
ARMul_Reset(state);
state->NextInstr = RESUME; // NOTE: This will be overwritten by LoadContext
state->Emulate = 3;
state->pc = state->Reg[15] = 0x00000000;
state->Reg[13] = 0x10000000; // Set stack pointer to the top of the stack
state->servaddr = 0xFFFF0000;
}
void
ns9750_mach_init (void *state, machine_config_t *this_mach)
{
#if 0
ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop);
/* FIXME:ARM926EJS uses LOW? */
state->lateabtSig = LOW;
state->Reg[1] = 552; //for NS9750
//state->Reg[1] = 627; //for NS9750
//state->Reg[1] = 196; //for NS9750
#endif
((generic_arch_t *)state)->set_regval_by_id(1, 552);
this_mach->mach_io_do_cycle = ns9750_io_do_cycle;
this_mach->mach_io_reset = ns9750_io_reset;
this_mach->mach_io_read_byte = ns9750_io_read_byte;
this_mach->mach_io_write_byte = ns9750_io_write_byte;
this_mach->mach_io_read_halfword = ns9750_io_read_halfword;
this_mach->mach_io_write_halfword = ns9750_io_write_halfword;
this_mach->mach_io_read_word = ns9750_io_read_word;
this_mach->mach_io_write_word = ns9750_io_write_word;
this_mach->mach_update_int = ns9750_update_int;
//this_mach->mach_set_intr = ns9750_set_intr;
//this_mach->mach_pending_intr = ns9750_pending_intr;
//this_mach->mach_update_intr = ns9750_update_intr;
//this_mach->mach_mem_read_byte = ns9750_mem_read_byte;
//this_mach->mach_mem_write_byte = ns9750_mem_write_byte;
//this_mach->state = (void *)state;
}
void
s3c2440_mach_init (void* arch_instance, machine_config_t * this_mach)
{
extern ARMul_State *state;
ARMul_SelectProcessor (state, ARM_v4_Prop);
/* ARM920T uses LOW */
state->lateabtSig = LOW;
this_mach->mach_io_do_cycle = s3c2440_io_do_cycle;
this_mach->mach_io_reset = s3c2440_io_reset;
this_mach->mach_io_read_byte = s3c2440_io_read_byte;
this_mach->mach_io_write_byte = s3c2440_io_write_byte;
this_mach->mach_io_read_halfword = s3c2440_io_read_halfword;
this_mach->mach_io_write_halfword = s3c2440_io_write_halfword;
this_mach->mach_io_read_word = s3c2440_io_read_word;
this_mach->mach_io_write_word = s3c2440_io_write_word;
this_mach->mach_update_int = s3c2440_update_int;
}
void
s3c2440_mach_init (ARMul_State * state, machine_config_t * this_mach)
{
ARMul_SelectProcessor (state, ARM_v4_Prop);
/* ARM920T uses LOW */
state->lateabtSig = LOW;
state->Reg[1] = 241; //ARCH_S3C2440
this_mach->mach_io_do_cycle = s3c2440_io_do_cycle;
this_mach->mach_io_reset = s3c2440_io_reset;
this_mach->mach_io_read_byte = s3c2440_io_read_byte;
this_mach->mach_io_write_byte = s3c2440_io_write_byte;
this_mach->mach_io_read_halfword = s3c2440_io_read_halfword;
this_mach->mach_io_write_halfword = s3c2440_io_write_halfword;
this_mach->mach_io_read_word = s3c2440_io_read_word;
this_mach->mach_io_write_word = s3c2440_io_write_word;
this_mach->mach_update_int = s3c2440_update_int;
}
void
cs89712_mach_init (void * arch_instance, machine_config_t * this_mach)
{
extern ARMul_State * state;
state->abort_model = 2;
ARMul_SelectProcessor (state, ARM_v4_Prop);
//chy 2004-05-09, set lateabtSig
state->lateabtSig = HIGH;
state->Reg[1] = 107; //for cdb89712 arch id
this_mach->mach_io_do_cycle = cs89712_io_do_cycle;
this_mach->mach_io_reset = cs89712_io_reset;
this_mach->mach_io_read_byte = cs89712_io_read_byte;
this_mach->mach_io_write_byte = cs89712_io_write_byte;
this_mach->mach_io_read_halfword = cs89712_io_read_halfword;
this_mach->mach_io_write_halfword = cs89712_io_write_halfword;
this_mach->mach_io_read_word = cs89712_io_read_word;
this_mach->mach_io_write_word = cs89712_io_write_word;
this_mach->mach_update_int = cs89712_update_int;
}
void
lh79520_mach_init (ARMul_State * state, machine_config_t * this_mach)
{
ARMul_SelectProcessor (state, ARM_v4_Prop);
state->lateabtSig = HIGH;
// state->Reg[1] = 999; //MACH_TYPE_LH79520EVB
state->Reg[1] = 997; //MACH_TYPE_LH79520LPD
this_mach->mach_io_do_cycle = lh79520_io_do_cycle;
this_mach->mach_io_reset = lh79520_io_reset;
this_mach->mach_io_read_byte = lh79520_io_read_byte;
this_mach->mach_io_write_byte = lh79520_io_write_byte;
this_mach->mach_io_read_halfword = lh79520_io_read_halfword;
this_mach->mach_io_write_halfword = lh79520_io_write_halfword;
this_mach->mach_io_read_word = lh79520_io_read_word;
this_mach->mach_io_write_word = lh79520_io_write_word;
this_mach->mach_update_int = lh79520_update_int;
state->mach_io.instr = (ARMword *) & io.intsr;
}
ARM_DynCom::ARM_DynCom(PrivilegeMode initial_mode) {
state = Common::make_unique<ARMul_State>();
ARMul_NewState(state.get());
ARMul_SelectProcessor(state.get(), ARM_v6_Prop | ARM_v5_Prop | ARM_v5e_Prop);
state->abort_model = ABORT_BASE_RESTORED;
state->bigendSig = LOW;
state->lateabtSig = LOW;
state->NirqSig = HIGH;
// Reset the core to initial state
ARMul_Reset(state.get());
state->Emulate = RUN;
// Switch to the desired privilege mode.
switch_mode(state.get(), initial_mode);
state->Reg[13] = 0x10000000; // Set stack pointer to the top of the stack
state->Reg[15] = 0x00000000;
}
ARM_Interpreter::ARM_Interpreter() {
m_state = new ARMul_State;
ARMul_EmulateInit();
ARMul_NewState(m_state);
m_state->abort_model = 0;
m_state->cpu = (cpu_config_t*)&s_arm11_cpu_info;
m_state->bigendSig = LOW;
ARMul_SelectProcessor(m_state, ARM_v6_Prop | ARM_v5_Prop | ARM_v5e_Prop);
m_state->lateabtSig = LOW;
mmu_init(m_state);
// Reset the core to initial state
ARMul_Reset(m_state);
m_state->NextInstr = 0;
m_state->Emulate = 3;
m_state->pc = m_state->Reg[15] = 0x00000000;
m_state->Reg[13] = 0x10000000; // Set stack pointer to the top of the stack
}
void
s3c2410x_mach_init (ARMul_State * state, machine_config_t * this_mach)
{
ARMul_SelectProcessor (state, ARM_v4_Prop);
this_mach->mach_io_do_cycle = s3c2410x_io_do_cycle;
this_mach->mach_io_reset = s3c2410x_io_reset;
this_mach->mach_io_read_byte = s3c2410x_io_read_byte;
this_mach->mach_io_write_byte = s3c2410x_io_write_byte;
this_mach->mach_io_read_halfword = s3c2410x_io_read_halfword;
this_mach->mach_io_write_halfword = s3c2410x_io_write_halfword;
this_mach->mach_io_read_word = s3c2410x_io_read_word;
this_mach->mach_io_write_word = s3c2410x_io_write_word;
this_mach->mach_update_int = s3c2410x_update_int;
this_mach->mach_set_intr = s3c2410x_set_ext_intr;
this_mach->mach_pending_intr = s3c2410x_pending_ext_intr;
this_mach->mach_update_intr = s3c2410x_update_intr;
this_mach->state = (void *) state;
}
void
s3c4510b_mach_init (void * arch_instance, machine_config_t * this_mach)
{
extern ARMul_State * state;
ARMul_SelectProcessor (state, ARM_v4_Prop);
state->lateabtSig = HIGH;
this_mach->mach_io_do_cycle = s3c4510b_io_do_cycle;
this_mach->mach_io_reset = s3c4510b_io_reset;
this_mach->mach_io_read_word = s3c4510b_io_read_word;
this_mach->mach_io_write_word = s3c4510b_io_write_word;
this_mach->mach_io_read_halfword = s3c4510b_io_read_halfword;
this_mach->mach_io_write_halfword = s3c4510b_io_write_halfword;
this_mach->mach_io_read_byte = s3c4510b_io_read_byte;
this_mach->mach_io_write_byte = s3c4510b_io_write_byte;
this_mach->mach_update_int = s3c4510b_update_int;
this_mach->mach_set_intr = s3c4510b_set_interrupt;
this_mach->mach_pending_intr = s3c4510b_pending_intr;
this_mach->mach_update_intr = s3c4510b_update_intr;
//this_mach->mach_mem_read_byte = s3c4510b_mem_read_byte;
//this_mach->mach_mem_write_byte = s3c4510b_mem_write_byte;
this_mach->state = (void *) state;
}
void
ep9312_mach_init (void* arch_instance, machine_config_t * this_mach)
{
extern ARMul_State * state;
ARMul_SelectProcessor (state, ARM_v4_Prop);
/* ARM920T uses LOW */
state->lateabtSig = LOW;
// state->Reg[1] = 282; //for EP9312 2.4.x arch id
state->Reg[1] = 451; //for EP9312 2.6.x arch id
//state->Reg[1] = 386; //for EP9315 2.4.x arch id
this_mach->mach_io_do_cycle = ep9312_io_do_cycle;
this_mach->mach_io_reset = ep9312_io_reset;
this_mach->mach_io_read_byte = ep9312_io_read_byte;
this_mach->mach_io_write_byte = ep9312_io_write_byte;
this_mach->mach_io_read_halfword = ep9312_io_read_halfword;
this_mach->mach_io_write_halfword = ep9312_io_write_halfword;
this_mach->mach_io_read_word = ep9312_io_read_word;
this_mach->mach_io_write_word = ep9312_io_write_word;
this_mach->mach_update_int = ep9312_update_int;
}
void
pxa270_mach_init (void *arch_instance, machine_config_t *mc)
{
//chy 2003-08-19, setprocessor
//chy 2005-09-19 add PXA27X_Prop
#if 0
ARMul_SelectProcessor (state,
ARM_XScale_Prop | ARM_v5_Prop | ARM_v5e_Prop |
ARM_PXA27X_Prop);
//chy 2004-05-09, set lateabtSig
state->lateabtSig = LOW;
state->Reg[1] = 406; /*mainstone machine id. */
#endif
((generic_arch_t *)arch_instance)->set_regval_by_id(1, 406); /*mainstone machine id. */
pxa270_io_reset ();
#if 0
/*added by ksh for energy estimation in 2004-11-26 */
state->energy.cccr = pxa270_io.cccr;
#endif
mc->mach_io_do_cycle = pxa270_io_do_cycle;
mc->mach_io_reset = pxa270_io_reset;
mc->mach_io_read_byte = pxa270_io_read_byte;
mc->mach_io_write_byte = pxa270_io_write_byte;
mc->mach_io_read_halfword = pxa270_io_read_halfword;
mc->mach_io_write_halfword = pxa270_io_write_halfword;
mc->mach_io_read_word = pxa270_io_read_word;
mc->mach_io_write_word = pxa270_io_write_word;
mc->mach_set_intr = pxa_set_intr;
mc->mach_pending_intr = pxa_pending_intr;
mc->mach_update_intr = pxa_update_intr;
// mc->state = (void *) state;
}
SIM_RC
sim_create_inferior (SIM_DESC sd ATTRIBUTE_UNUSED,
struct bfd * abfd,
char * const *argv,
char * const *env)
{
int argvlen = 0;
int mach;
char **arg;
init ();
if (abfd != NULL)
{
ARMul_SetPC (state, bfd_get_start_address (abfd));
mach = bfd_get_mach (abfd);
}
else
{
ARMul_SetPC (state, 0); /* ??? */
mach = 0;
}
#ifdef MODET
if (abfd != NULL && (bfd_get_start_address (abfd) & 1))
SETT;
#endif
switch (mach)
{
default:
(*sim_callback->printf_filtered)
(sim_callback,
"Unknown machine type '%d'; please update sim_create_inferior.\n",
mach);
/* fall through */
case 0:
/* We wouldn't set the machine type with earlier toolchains, so we
explicitly select a processor capable of supporting all ARMs in
32bit mode. */
ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_v6_Prop);
break;
case bfd_mach_arm_XScale:
ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop | ARM_v6_Prop);
break;
case bfd_mach_arm_iWMMXt2:
case bfd_mach_arm_iWMMXt:
{
extern int SWI_vector_installed;
ARMword i;
if (! SWI_vector_installed)
{
/* Intialise the hardware vectors to zero. */
if (! SWI_vector_installed)
for (i = ARMul_ResetV; i <= ARMFIQV; i += 4)
ARMul_WriteWord (state, i, 0);
/* ARM_WriteWord will have detected the write to the SWI vector,
but we want SWI_vector_installed to remain at 0 so that thumb
mode breakpoints will work. */
SWI_vector_installed = 0;
}
}
ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop | ARM_iWMMXt_Prop);
break;
case bfd_mach_arm_ep9312:
ARMul_SelectProcessor (state, ARM_v4_Prop | ARM_ep9312_Prop);
break;
case bfd_mach_arm_5:
if (bfd_family_coff (abfd))
{
/* This is a special case in order to support COFF based ARM toolchains.
The COFF header does not have enough room to store all the different
kinds of ARM cpu, so the XScale, v5T and v5TE architectures all default
to v5. (See coff_set_flags() in bdf/coffcode.h). So if we see a v5
machine type here, we assume it could be any of the above architectures
and so select the most feature-full. */
ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop);
break;
}
/* Otherwise drop through. */
case bfd_mach_arm_5T:
ARMul_SelectProcessor (state, ARM_v5_Prop);
break;
case bfd_mach_arm_5TE:
ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop);
break;
case bfd_mach_arm_4:
case bfd_mach_arm_4T:
ARMul_SelectProcessor (state, ARM_v4_Prop);
break;
case bfd_mach_arm_3:
case bfd_mach_arm_3M:
ARMul_SelectProcessor (state, ARM_Lock_Prop);
break;
case bfd_mach_arm_2:
case bfd_mach_arm_2a:
ARMul_SelectProcessor (state, ARM_Fix26_Prop);
break;
}
memset (& info, 0, sizeof (info));
INIT_DISASSEMBLE_INFO (info, stdout, op_printf);
info.read_memory_func = sim_dis_read;
info.arch = bfd_get_arch (abfd);
info.mach = bfd_get_mach (abfd);
info.endian_code = BFD_ENDIAN_LITTLE;
if (info.mach == 0)
info.arch = bfd_arch_arm;
disassemble_init_for_target (& info);
if (argv != NULL)
{
/* Set up the command line by laboriously stringing together
the environment carefully picked apart by our caller. */
/* Free any old stuff. */
if (state->CommandLine != NULL)
{
free (state->CommandLine);
state->CommandLine = NULL;
}
/* See how much we need. */
for (arg = argv; *arg != NULL; arg++)
argvlen += strlen (*arg) + 1;
/* Allocate it. */
state->CommandLine = malloc (argvlen + 1);
if (state->CommandLine != NULL)
{
arg = argv;
state->CommandLine[0] = '\0';
for (arg = argv; *arg != NULL; arg++)
{
strcat (state->CommandLine, *arg);
strcat (state->CommandLine, " ");
}
}
}
if (env != NULL)
{
/* Now see if there's a MEMSIZE spec in the environment. */
while (*env)
{
if (strncmp (*env, "MEMSIZE=", sizeof ("MEMSIZE=") - 1) == 0)
{
char *end_of_num;
/* Set up memory limit. */
state->MemSize =
strtoul (*env + sizeof ("MEMSIZE=") - 1, &end_of_num, 0);
}
env++;
}
}
return SIM_RC_OK;
}