/**
* Write to a MMIO register.
*
* @returns VBox status code suitable for scheduling.
* @param pDevIns The device instance.
* @param pvUser A user argument (ignored).
* @param GCPhysAddr The physical address being written to. (This is within our MMIO memory range.)
* @param pv Pointer to the data being written.
* @param cb The size of the data being written.
*/
PDMBOTHCBDECL(int) ox958MmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
{
PDEVOX958 pThis = PDMINS_2_DATA(pDevIns, PDEVOX958);
uint32_t offReg = (GCPhysAddr - pThis->GCPhysMMIO);
int rc = VINF_SUCCESS;
RT_NOREF1(pvUser);
if (offReg < OX958_REG_UART_REGION_OFFSET)
{
const uint32_t u32 = *(const uint32_t *)pv;
Assert(cb == 4);
switch (offReg)
{
case OX958_REG_UART_IRQ_ENABLE:
ASMAtomicOrU32(&pThis->u32RegIrqEnGlob, u32);
ox958IrqUpdate(pThis);
break;
case OX958_REG_UART_IRQ_DISABLE:
ASMAtomicAndU32(&pThis->u32RegIrqEnGlob, ~u32);
ox958IrqUpdate(pThis);
break;
case OX958_REG_UART_WAKE_IRQ_ENABLE:
ASMAtomicOrU32(&pThis->u32RegIrqEnWake, u32);
break;
case OX958_REG_UART_WAKE_IRQ_DISABLE:
ASMAtomicAndU32(&pThis->u32RegIrqEnWake, ~u32);
break;
case OX958_REG_UART_IRQ_STS: /* Readonly */
case OX958_REG_CC_REV_ID: /* Readonly */
case OX958_REG_UART_CNT: /* Readonly */
default:
rc = VINF_SUCCESS;
}
}
else
{
/* Figure out the UART accessed from the offset. */
offReg -= OX958_REG_UART_REGION_OFFSET;
uint32_t iUart = offReg / OX958_REG_UART_REGION_SIZE;
uint32_t offUartReg = offReg % OX958_REG_UART_REGION_SIZE;
if (iUart < pThis->cUarts)
{
POX958UART pUart = &pThis->aUarts[iUart];
rc = ox958UartRegWrite(pThis, pUart, offUartReg, pv, cb);
if (rc == VINF_IOM_R3_IOPORT_WRITE)
rc = VINF_IOM_R3_MMIO_WRITE;
}
}
return rc;
}
RTDECL(int) RTSemEventMultiReset(RTSEMEVENTMULTI hEventMultiSem)
{
PRTSEMEVENTMULTIINTERNAL pThis = (PRTSEMEVENTMULTIINTERNAL)hEventMultiSem;
RT_ASSERT_PREEMPT_CPUID_VAR();
AssertPtrReturn(pThis, VERR_INVALID_HANDLE);
AssertMsgReturn(pThis->u32Magic == RTSEMEVENTMULTI_MAGIC,
("pThis=%p u32Magic=%#x\n", pThis, pThis->u32Magic),
VERR_INVALID_HANDLE);
RT_ASSERT_INTS_ON();
rtR0SemEventMultiSolRetain(pThis);
rtR0SemSolWaitEnterMutexWithUnpinningHack(&pThis->Mtx);
Assert(pThis->u32Magic == RTSEMEVENTMULTI_MAGIC);
/*
* Do the job (could be done without the lock, but play safe).
*/
ASMAtomicAndU32(&pThis->fStateAndGen, ~RTSEMEVENTMULTISOL_STATE_MASK);
mutex_exit(&pThis->Mtx);
rtR0SemEventMultiSolRelease(pThis);
RT_ASSERT_PREEMPT_CPUID();
return VINF_SUCCESS;
}
RTDECL(int) RTSemEventMultiDestroy(RTSEMEVENTMULTI hEventMultiSem)
{
PRTSEMEVENTMULTIINTERNAL pThis = (PRTSEMEVENTMULTIINTERNAL)hEventMultiSem;
if (pThis == NIL_RTSEMEVENTMULTI)
return VINF_SUCCESS;
AssertPtrReturn(pThis, VERR_INVALID_HANDLE);
AssertMsgReturn(pThis->u32Magic == RTSEMEVENTMULTI_MAGIC, ("pThis=%p u32Magic=%#x\n", pThis, pThis->u32Magic), VERR_INVALID_HANDLE);
Assert(pThis->cRefs > 0);
RT_ASSERT_INTS_ON();
lck_spin_lock(pThis->pSpinlock);
ASMAtomicWriteU32(&pThis->u32Magic, ~RTSEMEVENTMULTI_MAGIC); /* make the handle invalid */
ASMAtomicAndU32(&pThis->fStateAndGen, RTSEMEVENTMULTIDARWIN_GEN_MASK);
if (pThis->fHaveBlockedThreads)
{
/* abort waiting threads. */
thread_wakeup_prim((event_t)pThis, FALSE /* all threads */, THREAD_RESTART);
}
lck_spin_unlock(pThis->pSpinlock);
rtR0SemEventMultiDarwinRelease(pThis);
return VINF_SUCCESS;
}
/**
* UART core IRQ request callback.
*
* @returns nothing.
* @param pDevIns The device instance.
* @param pUart The UART requesting an IRQ update.
* @param iLUN The UART index.
* @param iLvl IRQ level requested.
*/
PDMBOTHCBDECL(void) ox958IrqReq(PPDMDEVINS pDevIns, PUARTCORE pUart, unsigned iLUN, int iLvl)
{
RT_NOREF(pUart);
PDEVOX958 pThis = PDMINS_2_DATA(pDevIns, PDEVOX958);
if (iLvl)
ASMAtomicOrU32(&pThis->u32RegIrqStsGlob, RT_BIT_32(iLUN));
else
ASMAtomicAndU32(&pThis->u32RegIrqStsGlob, ~RT_BIT_32(iLUN));
ox958IrqUpdate(pThis);
}
RTDECL(int) RTSemEventMultiReset(RTSEMEVENTMULTI hEventMultiSem)
{
PRTSEMEVENTMULTIINTERNAL pThis = (PRTSEMEVENTMULTIINTERNAL)hEventMultiSem;
AssertPtrReturn(pThis, VERR_INVALID_HANDLE);
AssertMsgReturn(pThis->u32Magic == RTSEMEVENTMULTI_MAGIC, ("pThis=%p u32Magic=%#x\n", pThis, pThis->u32Magic), VERR_INVALID_HANDLE);
RT_ASSERT_PREEMPT_CPUID_VAR();
RT_ASSERT_INTS_ON();
rtR0SemEventMultiDarwinRetain(pThis);
lck_spin_lock(pThis->pSpinlock);
ASMAtomicAndU32(&pThis->fStateAndGen, ~RTSEMEVENTMULTIDARWIN_STATE_MASK);
lck_spin_unlock(pThis->pSpinlock);
rtR0SemEventMultiDarwinRelease(pThis);
RT_ASSERT_PREEMPT_CPUID();
return VINF_SUCCESS;
}
RTDECL(int) RTSemEventMultiReset(RTSEMEVENTMULTI hEventMultiSem)
{
/*
* Validate input.
*/
PRTSEMEVENTMULTIINTERNAL pThis = (PRTSEMEVENTMULTIINTERNAL)hEventMultiSem;
if (!pThis)
return VERR_INVALID_PARAMETER;
AssertPtrReturn(pThis, VERR_INVALID_PARAMETER);
AssertMsgReturn(pThis->u32Magic == RTSEMEVENTMULTI_MAGIC, ("%p u32Magic=%RX32\n", pThis, pThis->u32Magic), VERR_INVALID_PARAMETER);
rtR0SemEventMultiLnxRetain(pThis);
/*
* Reset it.
*/
ASMAtomicAndU32(&pThis->fStateAndGen, ~RTSEMEVENTMULTILNX_STATE_MASK);
rtR0SemEventMultiLnxRelease(pThis);
return VINF_SUCCESS;
}
RTDECL(int) RTSemEventMultiDestroy(RTSEMEVENTMULTI hEventMultiSem)
{
/*
* Validate input.
*/
PRTSEMEVENTMULTIINTERNAL pThis = (PRTSEMEVENTMULTIINTERNAL)hEventMultiSem;
if (pThis == NIL_RTSEMEVENTMULTI)
return VINF_SUCCESS;
AssertPtrReturn(pThis, VERR_INVALID_PARAMETER);
AssertMsgReturn(pThis->u32Magic == RTSEMEVENTMULTI_MAGIC, ("%p u32Magic=%RX32\n", pThis, pThis->u32Magic), VERR_INVALID_PARAMETER);
Assert(pThis->cRefs > 0);
/*
* Invalidate it and signal the object just in case.
*/
ASMAtomicWriteU32(&pThis->u32Magic, ~RTSEMEVENTMULTI_MAGIC);
ASMAtomicAndU32(&pThis->fStateAndGen, RTSEMEVENTMULTIBSD_GEN_MASK);
rtR0SemBsdBroadcast(pThis);
rtR0SemEventMultiBsdRelease(pThis);
return VINF_SUCCESS;
}
RTDECL(int) RTSemEventMultiDestroy(RTSEMEVENTMULTI hEventMultiSem)
{
PRTSEMEVENTMULTIINTERNAL pThis = (PRTSEMEVENTMULTIINTERNAL)hEventMultiSem;
if (pThis == NIL_RTSEMEVENTMULTI)
return VINF_SUCCESS;
AssertPtrReturn(pThis, VERR_INVALID_HANDLE);
AssertMsgReturn(pThis->u32Magic == RTSEMEVENTMULTI_MAGIC, ("pThis=%p u32Magic=%#x\n", pThis, pThis->u32Magic), VERR_INVALID_HANDLE);
AssertMsgReturn(pThis->cRefs > 0, ("pThis=%p cRefs=%d\n", pThis, pThis->cRefs), VERR_INVALID_HANDLE);
RT_ASSERT_INTS_ON();
mutex_enter(&pThis->Mtx);
/* Invalidate the handle and wake up all threads that might be waiting on the semaphore. */
Assert(pThis->u32Magic == RTSEMEVENTMULTI_MAGIC);
ASMAtomicWriteU32(&pThis->u32Magic, RTSEMEVENTMULTI_MAGIC_DEAD);
ASMAtomicAndU32(&pThis->fStateAndGen, RTSEMEVENTMULTISOL_GEN_MASK);
cv_broadcast(&pThis->Cnd);
/* Drop the reference from RTSemEventMultiCreateEx. */
mutex_exit(&pThis->Mtx);
rtR0SemEventMultiSolRelease(pThis);
return VINF_SUCCESS;
}
/**
* Leaves a critical section entered with PDMCritSectEnter().
*
* @param pCritSect The PDM critical section to leave.
*/
VMMDECL(void) PDMCritSectLeave(PPDMCRITSECT pCritSect)
{
AssertMsg(pCritSect->s.Core.u32Magic == RTCRITSECT_MAGIC, ("%p %RX32\n", pCritSect, pCritSect->s.Core.u32Magic));
Assert(pCritSect->s.Core.u32Magic == RTCRITSECT_MAGIC);
/* Check for NOP sections before asserting ownership. */
if (pCritSect->s.Core.fFlags & RTCRITSECT_FLAGS_NOP)
return;
/*
* Always check that the caller is the owner (screw performance).
*/
RTNATIVETHREAD const hNativeSelf = pdmCritSectGetNativeSelf(pCritSect);
AssertReleaseMsgReturnVoid(pCritSect->s.Core.NativeThreadOwner == hNativeSelf,
("%p %s: %p != %p; cLockers=%d cNestings=%d\n", pCritSect, R3STRING(pCritSect->s.pszName),
pCritSect->s.Core.NativeThreadOwner, hNativeSelf,
pCritSect->s.Core.cLockers, pCritSect->s.Core.cNestings));
Assert(pCritSect->s.Core.cNestings >= 1);
/*
* Nested leave.
*/
if (pCritSect->s.Core.cNestings > 1)
{
ASMAtomicDecS32(&pCritSect->s.Core.cNestings);
Assert(pCritSect->s.Core.cNestings >= 1);
ASMAtomicDecS32(&pCritSect->s.Core.cLockers);
Assert(pCritSect->s.Core.cLockers >= 0);
return;
}
#ifdef IN_RING0
# if 0 /** @todo Make SUPSemEventSignal interrupt safe (handle table++) and enable this for: defined(RT_OS_LINUX) || defined(RT_OS_OS2) */
if (1) /* SUPSemEventSignal is safe */
# else
if (ASMIntAreEnabled())
# endif
#endif
#if defined(IN_RING3) || defined(IN_RING0)
{
/*
* Leave for real.
*/
/* update members. */
# ifdef IN_RING3
RTSEMEVENT hEventToSignal = pCritSect->s.EventToSignal;
pCritSect->s.EventToSignal = NIL_RTSEMEVENT;
# if defined(PDMCRITSECT_STRICT)
if (pCritSect->s.Core.pValidatorRec->hThread != NIL_RTTHREAD)
RTLockValidatorRecExclReleaseOwnerUnchecked(pCritSect->s.Core.pValidatorRec);
# endif
Assert(!pCritSect->s.Core.pValidatorRec || pCritSect->s.Core.pValidatorRec->hThread == NIL_RTTHREAD);
# endif
ASMAtomicAndU32(&pCritSect->s.Core.fFlags, ~PDMCRITSECT_FLAGS_PENDING_UNLOCK);
ASMAtomicWriteHandle(&pCritSect->s.Core.NativeThreadOwner, NIL_RTNATIVETHREAD);
ASMAtomicDecS32(&pCritSect->s.Core.cNestings);
Assert(pCritSect->s.Core.cNestings == 0);
/* stop and decrement lockers. */
STAM_PROFILE_ADV_STOP(&pCritSect->s.StatLocked, l);
ASMCompilerBarrier();
if (ASMAtomicDecS32(&pCritSect->s.Core.cLockers) >= 0)
{
/* Someone is waiting, wake up one of them. */
SUPSEMEVENT hEvent = (SUPSEMEVENT)pCritSect->s.Core.EventSem;
PSUPDRVSESSION pSession = pCritSect->s.CTX_SUFF(pVM)->pSession;
int rc = SUPSemEventSignal(pSession, hEvent);
AssertRC(rc);
}
# ifdef IN_RING3
/* Signal exit event. */
if (hEventToSignal != NIL_RTSEMEVENT)
{
LogBird(("Signalling %#x\n", hEventToSignal));
int rc = RTSemEventSignal(hEventToSignal);
AssertRC(rc);
}
# endif
# if defined(DEBUG_bird) && defined(IN_RING0)
VMMTrashVolatileXMMRegs();
# endif
}
#endif /* IN_RING3 || IN_RING0 */
#ifdef IN_RING0
else
#endif
#if defined(IN_RING0) || defined(IN_RC)
{
/*
* Try leave it.
*/
if (pCritSect->s.Core.cLockers == 0)
{
ASMAtomicWriteS32(&pCritSect->s.Core.cNestings, 0);
RTNATIVETHREAD hNativeThread = pCritSect->s.Core.NativeThreadOwner;
ASMAtomicAndU32(&pCritSect->s.Core.fFlags, ~PDMCRITSECT_FLAGS_PENDING_UNLOCK);
STAM_PROFILE_ADV_STOP(&pCritSect->s.StatLocked, l);
ASMAtomicWriteHandle(&pCritSect->s.Core.NativeThreadOwner, NIL_RTNATIVETHREAD);
if (ASMAtomicCmpXchgS32(&pCritSect->s.Core.cLockers, -1, 0))
return;
/* darn, someone raced in on us. */
ASMAtomicWriteHandle(&pCritSect->s.Core.NativeThreadOwner, hNativeThread);
STAM_PROFILE_ADV_START(&pCritSect->s.StatLocked, l);
Assert(pCritSect->s.Core.cNestings == 0);
ASMAtomicWriteS32(&pCritSect->s.Core.cNestings, 1);
}
ASMAtomicOrU32(&pCritSect->s.Core.fFlags, PDMCRITSECT_FLAGS_PENDING_UNLOCK);
/*
* Queue the request.
*/
PVM pVM = pCritSect->s.CTX_SUFF(pVM); AssertPtr(pVM);
PVMCPU pVCpu = VMMGetCpu(pVM); AssertPtr(pVCpu);
uint32_t i = pVCpu->pdm.s.cQueuedCritSectLeaves++;
LogFlow(("PDMCritSectLeave: [%d]=%p => R3\n", i, pCritSect));
AssertFatal(i < RT_ELEMENTS(pVCpu->pdm.s.apQueuedCritSectsLeaves));
pVCpu->pdm.s.apQueuedCritSectsLeaves[i] = MMHyperCCToR3(pVM, pCritSect);
VMCPU_FF_SET(pVCpu, VMCPU_FF_PDM_CRITSECT);
VMCPU_FF_SET(pVCpu, VMCPU_FF_TO_R3);
STAM_REL_COUNTER_INC(&pVM->pdm.s.StatQueuedCritSectLeaves);
STAM_REL_COUNTER_INC(&pCritSect->s.StatContentionRZUnlock);
}
#endif /* IN_RING0 || IN_RC */
}
