void nandflash_hw_init(void)
{
unsigned int reg;
/* Configure nand pins */
const struct pio_desc nand_pins_lo[] = {
{"NANDOE", AT91C_PIN_PD(0), 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDWE", AT91C_PIN_PD(1), 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDALE", AT91C_PIN_PD(2), 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDCLE", AT91C_PIN_PD(3), 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDCS", CONFIG_SYS_NAND_ENABLE_PIN, 1, PIO_PULLUP, PIO_OUTPUT},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA);
reg |= AT91C_EBI_CS3A_SM;
reg &= ~AT91C_EBI_NFD0_ON_D16; /* nandflash connect to D0~D15 */
reg |= AT91C_EBI_DRV; /* according to IAR verification package */
writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA);
/* Configure SMC CS3 */
writel((AT91C_SMC_NWESETUP_(1)
| AT91C_SMC_NCS_WRSETUP_(0)
| AT91C_SMC_NRDSETUP_(3)
| AT91C_SMC_NCS_RDSETUP_(0)),
AT91C_BASE_SMC + SMC_SETUP3);
writel((AT91C_SMC_NWEPULSE_(3)
| AT91C_SMC_NCS_WRPULSE_(5)
| AT91C_SMC_NRDPULSE_(4)
| AT91C_SMC_NCS_RDPULSE_(6)),
AT91C_BASE_SMC + SMC_PULSE3);
writel((AT91C_SMC_NWECYCLE_(5)
| AT91C_SMC_NRDCYCLE_(8)),
AT91C_BASE_SMC + SMC_CYCLE3);
writel((AT91C_SMC_READMODE
| AT91C_SMC_WRITEMODE
| AT91C_SMC_NWAITM_NWAIT_DISABLE
| AT91C_SMC_DBW_WIDTH_BITS_8
| AT91_SMC_TDF_(1)),
AT91C_BASE_SMC + SMC_CTRL3);
/* Configure the nand controller pins*/
writel((1 << AT91C_ID_PIOC_D), (PMC_PCER + AT91C_BASE_PMC));
pio_configure(nand_pins_lo);
}
void nandflash_hw_init(void)
{
unsigned int reg;
/* Configure NANDFlash pins*/
const struct pio_desc nand_pins[] = {
{"NANDALE", AT91C_PIN_PB(2), 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDCLE", AT91C_PIN_PB(3), 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDOE", AT91C_PIN_PB(4), 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDWE", AT91C_PIN_PB(5), 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDCS", CONFIG_SYS_NAND_ENABLE_PIN, 1, PIO_PULLUP, PIO_OUTPUT},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
/* Setup Smart Media, first enable the address range of CS3 in HMATRIX user interface */
reg = readl(AT91C_BASE_CCFG + CCFG_EBI0CSA);
reg |= AT91C_EBI_CS3A_SM;
writel(reg, AT91C_BASE_CCFG + CCFG_EBI0CSA);
/* Configure SMC CS3 */
writel((AT91C_SMC_NWESETUP_(1)
| AT91C_SMC_NCS_WRSETUP_(0)
| AT91C_SMC_NRDSETUP_(1)
| AT91C_SMC_NCS_RDSETUP_(0)),
AT91C_BASE_SMC + SMC_SETUP3);
writel((AT91C_SMC_NWEPULSE_(3)
| AT91C_SMC_NCS_WRPULSE_(3)
| AT91C_SMC_NRDPULSE_(3)
| AT91C_SMC_NCS_RDPULSE_(3)),
AT91C_BASE_SMC + SMC_PULSE3);
writel((AT91C_SMC_NWECYCLE_(5)
| AT91C_SMC_NRDCYCLE_(5)),
AT91C_BASE_SMC + SMC_CYCLE3);
writel((AT91C_SMC_READMODE
| AT91C_SMC_WRITEMODE
| AT91C_SMC_NWAITM_NWAIT_DISABLE
| AT91C_SMC_DBW_WIDTH_BITS_8
| AT91_SMC_TDF_(2)),
AT91C_BASE_SMC + SMC_CTRL3);
/* Configure the NANDFlash pins */
pmc_enable_periph_clock(AT91C_ID_PIOB);
pio_configure(nand_pins);
}
void nandflash_hw_init(void)
{
unsigned int reg;
/* Configure PIOs */
const struct pio_desc nand_pins[] = {
{"NANDCS", CONFIG_SYS_NAND_ENABLE_PIN, 1, PIO_PULLUP, PIO_OUTPUT},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
/* Setup Smart Media, first enable the address range of CS3
* in HMATRIX user interface
* EBI IO in 1.8V mode */
reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA);
reg |= AT91C_EBI_CS3A_SM;
reg &= ~AT91C_VDDIOM_SEL_33V;
writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA);
/* Configure SMC CS3 */
writel((AT91C_SMC_NWESETUP_(2)
| AT91C_SMC_NCS_WRSETUP_(0)
| AT91C_SMC_NRDSETUP_(2)
| AT91C_SMC_NCS_RDSETUP_(0)),
AT91C_BASE_SMC + SMC_SETUP3);
writel((AT91C_SMC_NWEPULSE_(4)
| AT91C_SMC_NCS_WRPULSE_(4)
| AT91C_SMC_NRDPULSE_(4)
| AT91C_SMC_NCS_RDPULSE_(4)),
AT91C_BASE_SMC + SMC_PULSE3);
writel((AT91C_SMC_NWECYCLE_(7)
| AT91C_SMC_NRDCYCLE_(7)),
AT91C_BASE_SMC + SMC_CYCLE3);
writel((AT91C_SMC_READMODE
| AT91C_SMC_WRITEMODE
| AT91C_SMC_NWAITM_NWAIT_DISABLE
| AT91C_SMC_DBW_WIDTH_BITS_16
| AT91_SMC_TDF_(3)),
AT91C_BASE_SMC + SMC_CTRL3);
/* Configure the PIO controll */
writel((1 << AT91C_ID_PIOC), (PMC_PCER + AT91C_BASE_PMC));
pio_configure(nand_pins);
}
void nandflash_hw_init(void)
{
unsigned int reg;
/* Setup Smart Media, first enable the address range of
* CS3 in HMATRIX user interface */
reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA);
reg |= AT91C_EBI_CS3A_SM;
writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA);
/* Configure SMC CS3 */
writel((AT91C_SMC_NWESETUP_(1)
| AT91C_SMC_NCS_WRSETUP_(0)
| AT91C_SMC_NRDSETUP_(1)
| AT91C_SMC_NCS_RDSETUP_(0)),
AT91C_BASE_SMC + SMC_SETUP3);
writel((AT91C_SMC_NWEPULSE_(3)
| AT91C_SMC_NCS_WRPULSE_(3)
| AT91C_SMC_NRDPULSE_(3)
| AT91C_SMC_NCS_RDPULSE_(3)),
AT91C_BASE_SMC + SMC_PULSE3);
writel((AT91C_SMC_NWECYCLE_(5)
| AT91C_SMC_NRDCYCLE_(5)),
AT91C_BASE_SMC + SMC_CYCLE3);
writel((AT91C_SMC_READMODE
| AT91C_SMC_WRITEMODE
/* AT91C_SMC_NWAITM_NWAIT_DISABLE */
| (0x0 << 5)
| AT91C_SMC_DBW_WIDTH_BITS_16
| AT91_SMC_TDF_(2)),
AT91C_BASE_SMC + SMC_CTRL3);
/* configure NAND pins */
/* {"NANDCS", AT91C_PIN_PC(14), 1, PIO_PULLUP, PIO_OUTPUT} */
writel((0x01 << 14), AT91C_BASE_PIOC + PIO_IDR(0));
writel((0x01 << 14), AT91C_BASE_PIOC + PIO_PPUDR(0));
writel((0x01 << 14), AT91C_BASE_PIOC + PIO_SODR(0));
writel((0x01 << 14), AT91C_BASE_PIOC + PIO_OER(0));
writel((0x01 << 14), AT91C_BASE_PIOC + PIO_PER(0));
/* enable PIOC clock */
writel((1 << AT91C_ID_PIOC), PMC_PCER + AT91C_BASE_PMC);
}
static void psram_hw_init(void)
{
unsigned short *addressMax = (unsigned short *)MICRON_8MB_ADDRESS_MAX;
const struct pio_desc psram_pins[] = {
{"CRE", CONFIG_SYS_PSRAM_DATA_ACCESS_PIN, 1, PIO_DEFAULT, PIO_OUTPUT},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
/* Configure SMC1 CS0 */
writel((AT91C_SMC_NWESETUP_(0)
| AT91C_SMC_NCS_WRSETUP_(0)
| AT91C_SMC_NRDSETUP_(0)
| AT91C_SMC_NCS_RDSETUP_(0)),
AT91C_BASE_SMC1 + SMC_SETUP0);
writel((AT91C_SMC_NWEPULSE_(4)
| AT91C_SMC_NCS_WRPULSE_(5)
| AT91C_SMC_NRDPULSE_(2)
| AT91C_SMC_NCS_RDPULSE_(5)),
AT91C_BASE_SMC1 + SMC_PULSE0);
writel((AT91C_SMC_NWECYCLE_(5)
| AT91C_SMC_NRDCYCLE_(7)),
AT91C_BASE_SMC1 + SMC_CYCLE0);
writel((AT91C_SMC_READMODE
| AT91C_SMC_WRITEMODE
| AT91C_SMC_BAT_BYTE_SELECT
| AT91C_SMC_DBW_WIDTH_BITS_16
| AT91C_SMC_PMEN
| AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES),
AT91C_BASE_SMC1 + SMC_CTRL0);
/* Configure psram pins */
pio_configure(psram_pins);
data_access_enable();
/* Enable page mode */
readl(addressMax);
readl(addressMax);
writel(MICRON_RCR, addressMax);
writel(MICRON_PAGE_MODE_ENABLE, addressMax);
}
void nandflash_hw_init(void)
{
unsigned int reg;
/* Configure Nand PINs */
const struct pio_desc nand_pins_hi[] = {
{"NANDOE", CONFIG_SYS_NAND_OE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDWE", CONFIG_SYS_NAND_WE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDALE", CONFIG_SYS_NAND_ALE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDCLE", CONFIG_SYS_NAND_CLE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDCS", CONFIG_SYS_NAND_ENABLE_PIN, 1, PIO_PULLUP, PIO_OUTPUT},
{"D0", AT91C_PIN_PD(6), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D1", AT91C_PIN_PD(7), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D2", AT91C_PIN_PD(8), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D3", AT91C_PIN_PD(9), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D4", AT91C_PIN_PD(10), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D5", AT91C_PIN_PD(11), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D6", AT91C_PIN_PD(12), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D7", AT91C_PIN_PD(13), 0, PIO_PULLUP, PIO_PERIPH_A},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
const struct pio_desc nand_pins_lo[] = {
{"NANDOE", CONFIG_SYS_NAND_OE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDWE", CONFIG_SYS_NAND_WE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDALE", CONFIG_SYS_NAND_ALE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDCLE", CONFIG_SYS_NAND_CLE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDCS", CONFIG_SYS_NAND_ENABLE_PIN, 1, PIO_PULLUP, PIO_OUTPUT},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA);
reg |= AT91C_EBI_CS3A_SM;
if (get_cm_rev() == 'A')
reg &= ~AT91C_EBI_NFD0_ON_D16;
else
reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16);
reg &= ~AT91C_EBI_DRV;
writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA);
/* Configure SMC CS3 */
writel((AT91C_SMC_NWESETUP_(1)
| AT91C_SMC_NCS_WRSETUP_(0)
| AT91C_SMC_NRDSETUP_(2)
| AT91C_SMC_NCS_RDSETUP_(0)),
AT91C_BASE_SMC + SMC_SETUP3);
writel((AT91C_SMC_NWEPULSE_(3)
| AT91C_SMC_NCS_WRPULSE_(5)
| AT91C_SMC_NRDPULSE_(4)
| AT91C_SMC_NCS_RDPULSE_(6)),
AT91C_BASE_SMC + SMC_PULSE3);
writel((AT91C_SMC_NWECYCLE_(5)
| AT91C_SMC_NRDCYCLE_(7)),
AT91C_BASE_SMC + SMC_CYCLE3);
writel((AT91C_SMC_READMODE
| AT91C_SMC_WRITEMODE
| AT91C_SMC_NWAITM_NWAIT_DISABLE
| AT91C_SMC_DBW_WIDTH_BITS_8
| AT91_SMC_TDF_(1)),
AT91C_BASE_SMC + SMC_CTRL3);
/* Configure the PIO controller */
if (get_cm_rev() == 'A')
pio_configure(nand_pins_lo);
else
pio_configure(nand_pins_hi);
pmc_enable_periph_clock(AT91C_ID_PIOC_D);
}