/**Function*************************************************************
Synopsis [Load the network into FPGA manager.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Fpga_Man_t * Abc_NtkToFpga( Abc_Ntk_t * pNtk, int fRecovery, float * pSwitching, int fLatchPaths, int fVerbose )
{
Fpga_Man_t * pMan;
ProgressBar * pProgress;
Fpga_Node_t * pNodeFpga;
Vec_Ptr_t * vNodes;
Abc_Obj_t * pNode, * pFanin, * pPrev;
float * pfArrivals;
int i;
assert( Abc_NtkIsStrash(pNtk) );
// start the mapping manager and set its parameters
pMan = Fpga_ManCreate( Abc_NtkCiNum(pNtk), Abc_NtkCoNum(pNtk), fVerbose );
if ( pMan == NULL )
return NULL;
Fpga_ManSetAreaRecovery( pMan, fRecovery );
Fpga_ManSetOutputNames( pMan, Abc_NtkCollectCioNames(pNtk, 1) );
pfArrivals = Abc_NtkGetCiArrivalFloats(pNtk);
if ( fLatchPaths )
{
for ( i = 0; i < Abc_NtkPiNum(pNtk); i++ )
pfArrivals[i] = -FPGA_FLOAT_LARGE;
}
Fpga_ManSetInputArrivals( pMan, pfArrivals );
// create PIs and remember them in the old nodes
Abc_NtkCleanCopy( pNtk );
Abc_AigConst1(pNtk)->pCopy = (Abc_Obj_t *)Fpga_ManReadConst1(pMan);
Abc_NtkForEachCi( pNtk, pNode, i )
{
pNodeFpga = Fpga_ManReadInputs(pMan)[i];
pNode->pCopy = (Abc_Obj_t *)pNodeFpga;
if ( pSwitching )
Fpga_NodeSetSwitching( pNodeFpga, pSwitching[pNode->Id] );
}
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Returns internal nodes used in the mapping.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Int_t * Llb_AigMap( Aig_Man_t * pAig, int nLutSize, int nLutMin )
{
extern Abc_Ntk_t * Abc_NtkFromAigPhase( Aig_Man_t * pMan );
extern If_Man_t * Abc_NtkToIf( Abc_Ntk_t * pNtk, If_Par_t * pPars );
extern void Gia_ManSetIfParsDefault( If_Par_t * pPars );
If_Par_t Pars, * pPars = &Pars;
If_Man_t * pIfMan;
If_Obj_t * pAnd;
Abc_Ntk_t * pNtk;
Abc_Obj_t * pNode;
Vec_Int_t * vNodes;
Aig_Obj_t * pObj;
int i;
// create ABC network
pNtk = Abc_NtkFromAigPhase( pAig );
assert( Abc_NtkIsStrash(pNtk) );
// derive mapping parameters
Gia_ManSetIfParsDefault( pPars );
pPars->nLutSize = nLutSize;
// get timing information
pPars->pTimesArr = Abc_NtkGetCiArrivalFloats(pNtk);
pPars->pTimesReq = NULL;
// perform LUT mapping
pIfMan = Abc_NtkToIf( pNtk, pPars );
if ( pIfMan == NULL )
{
Abc_NtkDelete( pNtk );
return NULL;
}
if ( !If_ManPerformMapping( pIfMan ) )
{
Abc_NtkDelete( pNtk );
If_ManStop( pIfMan );
return NULL;
}
// mark nodes in the AIG used in the mapping
Aig_ManCleanMarkA( pAig );
Aig_ManForEachNode( pAig, pObj, i )
{
pNode = (Abc_Obj_t *)pObj->pData;
if ( pNode == NULL )
continue;
pAnd = (If_Obj_t *)pNode->pCopy;
if ( pAnd == NULL )
continue;
if ( pAnd->nRefs > 0 && (int)If_ObjCutBest(pAnd)->nLeaves >= nLutMin )
pObj->fMarkA = 1;
}