/**Function*************************************************************
Synopsis [Computes initial values of the new latches.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Int_t * Abc_NtkRetimeInitialValues( Abc_Ntk_t * pNtkCone, Vec_Int_t * vValues, int fVerbose )
{
Vec_Int_t * vSolution;
Abc_Ntk_t * pNtkMiter, * pNtkLogic;
int RetValue;
abctime clk;
if ( pNtkCone == NULL )
return Vec_IntDup( vValues );
// convert the target network to AIG
pNtkLogic = Abc_NtkDup( pNtkCone );
Abc_NtkToAig( pNtkLogic );
// get the miter
pNtkMiter = Abc_NtkCreateTarget( pNtkLogic, pNtkLogic->vCos, vValues );
if ( fVerbose )
printf( "The miter for initial state computation has %d AIG nodes. ", Abc_NtkNodeNum(pNtkMiter) );
// solve the miter
clk = Abc_Clock();
RetValue = Abc_NtkMiterSat( pNtkMiter, (ABC_INT64_T)500000, (ABC_INT64_T)50000000, 0, NULL, NULL );
if ( fVerbose )
{ ABC_PRT( "SAT solving time", Abc_Clock() - clk ); }
// analyze the result
if ( RetValue == 1 )
printf( "Abc_NtkRetimeInitialValues(): The problem is unsatisfiable. DC latch values are used.\n" );
else if ( RetValue == -1 )
printf( "Abc_NtkRetimeInitialValues(): The SAT problem timed out. DC latch values are used.\n" );
else if ( !Abc_NtkRetimeVerifyModel( pNtkCone, vValues, pNtkMiter->pModel ) )
printf( "Abc_NtkRetimeInitialValues(): The computed counter-example is incorrect.\n" );
// set the values of the latches
vSolution = RetValue? NULL : Vec_IntAllocArray( pNtkMiter->pModel, Abc_NtkPiNum(pNtkLogic) );
pNtkMiter->pModel = NULL;
Abc_NtkDelete( pNtkMiter );
Abc_NtkDelete( pNtkLogic );
return vSolution;
}
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Converts old ABC network into new ABC network.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Nwk_Man_t * Abc_NtkToNtkNew( Abc_Ntk_t * pNtk )
{
Vec_Ptr_t * vNodes;
Nwk_Man_t * pNtkNew;
Nwk_Obj_t * pObjNew;
Abc_Obj_t * pObj, * pFanin;
int i, k;
if ( !Abc_NtkIsLogic(pNtk) )
{
fprintf( stdout, "This is not a logic network.\n" );
return 0;
}
// convert into the AIG
if ( !Abc_NtkToAig(pNtk) )
{
fprintf( stdout, "Converting to AIGs has failed.\n" );
return 0;
}
assert( Abc_NtkHasAig(pNtk) );
// construct the network
pNtkNew = Nwk_ManAlloc();
pNtkNew->pName = Extra_UtilStrsav( pNtk->pName );
pNtkNew->pSpec = Extra_UtilStrsav( pNtk->pSpec );
Abc_NtkForEachCi( pNtk, pObj, i )
pObj->pCopy = (Abc_Obj_t *)Nwk_ManCreateCi( pNtkNew, Abc_ObjFanoutNum(pObj) );
vNodes = Abc_NtkDfs( pNtk, 1 );
Vec_PtrForEachEntry( Abc_Obj_t *, vNodes, pObj, i )
{
pObjNew = Nwk_ManCreateNode( pNtkNew, Abc_ObjFaninNum(pObj), Abc_ObjFanoutNum(pObj) );
Abc_ObjForEachFanin( pObj, pFanin, k )
Nwk_ObjAddFanin( pObjNew, (Nwk_Obj_t *)pFanin->pCopy );
pObjNew->pFunc = Hop_Transfer( (Hop_Man_t *)pNtk->pManFunc, pNtkNew->pManHop, (Hop_Obj_t *)pObj->pData, Abc_ObjFaninNum(pObj) );
pObj->pCopy = (Abc_Obj_t *)pObjNew;
}
/**Function*************************************************************
Synopsis [Derives GIA manager using special pins to denote box boundaries.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Gia_Man_t * Abc_NtkTestPinDeriveGia( Abc_Ntk_t * pNtk, int fWhiteBoxOnly, int fVerbose )
{
Gia_Man_t * pTemp;
Gia_Man_t * pGia = NULL;
Vec_Ptr_t * vNodes;
Abc_Obj_t * pObj, * pFanin;
int i, k, iPinLit = 0;
// prepare logic network
assert( Abc_NtkIsLogic(pNtk) );
Abc_NtkToAig( pNtk );
// construct GIA
Abc_NtkFillTemp( pNtk );
pGia = Gia_ManStart( Abc_NtkObjNumMax(pNtk) );
Gia_ManHashAlloc( pGia );
// create primary inputs
Abc_NtkForEachCi( pNtk, pObj, i )
pObj->iTemp = Gia_ManAppendCi(pGia);
// create internal nodes in a topologic order from white boxes
vNodes = Abc_NtkDfs( pNtk, 0 );
Vec_PtrForEachEntry( Abc_Obj_t *, vNodes, pObj, i )
{
// input side
if ( !fWhiteBoxOnly || Abc_NodeIsWhiteBox(pObj) )
{
// create special pintype for this node
iPinLit = Gia_ManAppendPinType( pGia, 1 );
// create input pins
Abc_ObjForEachFanin( pObj, pFanin, k )
pFanin->iTemp = Gia_ManAppendAnd( pGia, pFanin->iTemp, iPinLit );
}
// perform GIA construction
pObj->iTemp = Abc_NtkTestTimNodeStrash( pGia, pObj );
// output side
if ( !fWhiteBoxOnly || Abc_NodeIsWhiteBox(pObj) )
{
// create special pintype for this node
iPinLit = Gia_ManAppendPinType( pGia, 1 );
// create output pins
pObj->iTemp = Gia_ManAppendAnd( pGia, pObj->iTemp, iPinLit );
}
}
Vec_PtrFree( vNodes );
// create primary outputs
Abc_NtkForEachCo( pNtk, pObj, i )
pObj->iTemp = Gia_ManAppendCo( pGia, Abc_ObjFanin0(pObj)->iTemp );
// finalize GIA
Gia_ManHashStop( pGia );
Gia_ManSetRegNum( pGia, 0 );
// clean up GIA
pGia = Gia_ManCleanup( pTemp = pGia );
Gia_ManStop( pTemp );
return pGia;
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Abc_NtkMfs( Abc_Ntk_t * pNtk, Mfs_Par_t * pPars )
{
extern Aig_Man_t * Abc_NtkToDar( Abc_Ntk_t * pNtk, int fExors, int fRegisters );
Bdc_Par_t Pars = {0}, * pDecPars = &Pars;
ProgressBar * pProgress;
Mfs_Man_t * p;
Abc_Obj_t * pObj;
Vec_Vec_t * vLevels;
Vec_Ptr_t * vNodes;
int i, k, nNodes, nFaninMax;
abctime clk = Abc_Clock(), clk2;
int nTotalNodesBeg = Abc_NtkNodeNum(pNtk);
int nTotalEdgesBeg = Abc_NtkGetTotalFanins(pNtk);
assert( Abc_NtkIsLogic(pNtk) );
nFaninMax = Abc_NtkGetFaninMax(pNtk);
if ( pPars->fResub )
{
if ( nFaninMax > 8 )
{
printf( "Nodes with more than %d fanins will not be processed.\n", 8 );
nFaninMax = 8;
}
}
else
{
if ( nFaninMax > MFS_FANIN_MAX )
{
printf( "Nodes with more than %d fanins will not be processed.\n", MFS_FANIN_MAX );
nFaninMax = MFS_FANIN_MAX;
}
}
// perform the network sweep
// Abc_NtkSweep( pNtk, 0 );
// convert into the AIG
if ( !Abc_NtkToAig(pNtk) )
{
fprintf( stdout, "Converting to AIGs has failed.\n" );
return 0;
}
assert( Abc_NtkHasAig(pNtk) );
// start the manager
p = Mfs_ManAlloc( pPars );
p->pNtk = pNtk;
p->nFaninMax = nFaninMax;
// precomputer power-aware metrics
if ( pPars->fPower )
{
extern Vec_Int_t * Abc_NtkPowerEstimate( Abc_Ntk_t * pNtk, int fProbOne );
if ( pPars->fResub )
p->vProbs = Abc_NtkPowerEstimate( pNtk, 0 );
else
p->vProbs = Abc_NtkPowerEstimate( pNtk, 1 );
#if 0
printf( "Total switching before = %7.2f.\n", Abc_NtkMfsTotalSwitching(pNtk) );
#else
p->TotalSwitchingBeg = Abc_NtkMfsTotalSwitching(pNtk);
#endif
}
if ( pNtk->pExcare )
{
Abc_Ntk_t * pTemp;
if ( Abc_NtkPiNum((Abc_Ntk_t *)pNtk->pExcare) != Abc_NtkCiNum(pNtk) )
printf( "The PI count of careset (%d) and logic network (%d) differ. Careset is not used.\n",
Abc_NtkPiNum((Abc_Ntk_t *)pNtk->pExcare), Abc_NtkCiNum(pNtk) );
else
{
pTemp = Abc_NtkStrash( (Abc_Ntk_t *)pNtk->pExcare, 0, 0, 0 );
p->pCare = Abc_NtkToDar( pTemp, 0, 0 );
Abc_NtkDelete( pTemp );
p->vSuppsInv = Aig_ManSupportsInverse( p->pCare );
}
}
if ( p->pCare != NULL )
printf( "Performing optimization with %d external care clauses.\n", Aig_ManCoNum(p->pCare) );
// prepare the BDC manager
if ( !pPars->fResub )
{
pDecPars->nVarsMax = (nFaninMax < 3) ? 3 : nFaninMax;
pDecPars->fVerbose = pPars->fVerbose;
p->vTruth = Vec_IntAlloc( 0 );
p->pManDec = Bdc_ManAlloc( pDecPars );
}
// label the register outputs
if ( p->pCare )
{
Abc_NtkForEachCi( pNtk, pObj, i )
pObj->pData = (void *)(ABC_PTRUINT_T)i;
}
// compute levels
Abc_NtkLevel( pNtk );
Abc_NtkStartReverseLevels( pNtk, pPars->nGrowthLevel );
// compute don't-cares for each node
nNodes = 0;
p->nTotalNodesBeg = nTotalNodesBeg;
p->nTotalEdgesBeg = nTotalEdgesBeg;
if ( pPars->fResub )
{
#if 0
printf( "TotalSwitching (%7.2f --> ", Abc_NtkMfsTotalSwitching(pNtk) );
#endif
if (pPars->fPower)
{
Abc_NtkMfsPowerResub( p, pPars);
} else
{
pProgress = Extra_ProgressBarStart( stdout, Abc_NtkObjNumMax(pNtk) );
Abc_NtkForEachNode( pNtk, pObj, i )
{
if ( p->pPars->nDepthMax && (int)pObj->Level > p->pPars->nDepthMax )
continue;
if ( Abc_ObjFaninNum(pObj) < 2 || Abc_ObjFaninNum(pObj) > nFaninMax )
continue;
if ( !p->pPars->fVeryVerbose )
Extra_ProgressBarUpdate( pProgress, i, NULL );
if ( pPars->fResub )
Abc_NtkMfsResub( p, pObj );
else
Abc_NtkMfsNode( p, pObj );
}
Extra_ProgressBarStop( pProgress );
#if 0
printf( " %7.2f )\n", Abc_NtkMfsTotalSwitching(pNtk) );
#endif
}
} else
/**Function*************************************************************
Synopsis [Write the network into file.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Io_WriteHie( Abc_Ntk_t * pNtk, char * pBaseName, char * pFileName )
{
Abc_Ntk_t * pNtkTemp, * pNtkResult, * pNtkBase = NULL;
// check if the current network is available
if ( pNtk == NULL )
{
fprintf( stdout, "Empty network.\n" );
return;
}
// read the base network
assert( Abc_NtkIsStrash(pNtk) || Abc_NtkIsLogic(pNtk) );
if ( Io_ReadFileType(pBaseName) == IO_FILE_BLIF )
pNtkBase = Io_ReadBlifMv( pBaseName, 0, 1 );
else if ( Io_ReadFileType(pBaseName) == IO_FILE_BLIFMV )
pNtkBase = Io_ReadBlifMv( pBaseName, 1, 1 );
else if ( Io_ReadFileType(pBaseName) == IO_FILE_VERILOG )
pNtkBase = Io_ReadVerilog( pBaseName, 1 );
else
fprintf( stderr, "Unknown input file format.\n" );
if ( pNtkBase == NULL )
return;
// flatten logic hierarchy if present
if ( Abc_NtkWhiteboxNum(pNtkBase) > 0 )
{
pNtkBase = Abc_NtkFlattenLogicHierarchy( pNtkTemp = pNtkBase );
if ( pNtkBase == NULL )
return;
Abc_NtkDelete( pNtkTemp );
}
// reintroduce the boxes into the netlist
if ( Io_ReadFileType(pBaseName) == IO_FILE_BLIFMV )
{
if ( Abc_NtkBlackboxNum(pNtkBase) > 0 )
{
printf( "Hierarchy writer does not support BLIF-MV with blackboxes.\n" );
Abc_NtkDelete( pNtkBase );
return;
}
// convert the current network to BLIF-MV
assert( !Abc_NtkIsNetlist(pNtk) );
pNtkResult = Abc_NtkToNetlist( pNtk );
if ( !Abc_NtkConvertToBlifMv( pNtkResult ) )
return;
// reintroduce the network
pNtkResult = Abc_NtkInsertBlifMv( pNtkBase, pNtkTemp = pNtkResult );
Abc_NtkDelete( pNtkTemp );
}
else if ( Abc_NtkBlackboxNum(pNtkBase) > 0 )
{
// derive the netlist
pNtkResult = Abc_NtkToNetlist( pNtk );
pNtkResult = Abc_NtkInsertNewLogic( pNtkBase, pNtkTemp = pNtkResult );
Abc_NtkDelete( pNtkTemp );
if ( pNtkResult )
printf( "Hierarchy writer reintroduced %d instances of blackboxes.\n", Abc_NtkBlackboxNum(pNtkBase) );
}
else
{
printf( "Warning: The output network does not contain blackboxes.\n" );
pNtkResult = Abc_NtkToNetlist( pNtk );
}
Abc_NtkDelete( pNtkBase );
if ( pNtkResult == NULL )
return;
// write the resulting network
if ( Io_ReadFileType(pFileName) == IO_FILE_BLIF )
{
if ( !Abc_NtkHasSop(pNtkResult) && !Abc_NtkHasMapping(pNtkResult) )
Abc_NtkToSop( pNtkResult, 0 );
Io_WriteBlif( pNtkResult, pFileName, 1 );
}
else if ( Io_ReadFileType(pFileName) == IO_FILE_VERILOG )
{
if ( !Abc_NtkHasAig(pNtkResult) && !Abc_NtkHasMapping(pNtkResult) )
Abc_NtkToAig( pNtkResult );
Io_WriteVerilog( pNtkResult, pFileName );
}
else if ( Io_ReadFileType(pFileName) == IO_FILE_BLIFMV )
{
Io_WriteBlifMv( pNtkResult, pFileName );
}
else
fprintf( stderr, "Unknown output file format.\n" );
Abc_NtkDelete( pNtkResult );
}
/**Function*************************************************************
Synopsis [Write the network into file.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Io_Write( Abc_Ntk_t * pNtk, char * pFileName, Io_FileType_t FileType )
{
Abc_Ntk_t * pNtkTemp, * pNtkCopy;
// check if the current network is available
if ( pNtk == NULL )
{
fprintf( stdout, "Empty network.\n" );
return;
}
// check if the file extension if given
if ( FileType == IO_FILE_NONE || FileType == IO_FILE_UNKNOWN )
{
fprintf( stdout, "The generic file writer requires a known file extension.\n" );
return;
}
// write the AIG formats
if ( FileType == IO_FILE_AIGER || FileType == IO_FILE_BAF )
{
if ( !Abc_NtkIsStrash(pNtk) )
{
fprintf( stdout, "Writing this format is only possible for structurally hashed AIGs.\n" );
return;
}
if ( FileType == IO_FILE_AIGER )
Io_WriteAiger( pNtk, pFileName, 1 );
else // if ( FileType == IO_FILE_BAF )
Io_WriteBaf( pNtk, pFileName );
return;
}
// write non-netlist types
if ( FileType == IO_FILE_CNF )
{
Io_WriteCnf( pNtk, pFileName, 0 );
return;
}
if ( FileType == IO_FILE_DOT )
{
Io_WriteDot( pNtk, pFileName );
return;
}
if ( FileType == IO_FILE_GML )
{
Io_WriteGml( pNtk, pFileName );
return;
}
/*
if ( FileType == IO_FILE_BLIFMV )
{
Io_WriteBlifMv( pNtk, pFileName );
return;
}
*/
// convert logic network into netlist
if ( FileType == IO_FILE_PLA )
{
if ( Abc_NtkLevel(pNtk) > 1 )
{
fprintf( stdout, "PLA writing is available for collapsed networks.\n" );
return;
}
if ( Abc_NtkIsComb(pNtk) )
pNtkTemp = Abc_NtkToNetlist( pNtk );
else
{
fprintf( stdout, "Latches are writen into the PLA file at PI/PO pairs.\n" );
pNtkCopy = Abc_NtkDup( pNtk );
Abc_NtkMakeComb( pNtkCopy );
pNtkTemp = Abc_NtkToNetlist( pNtk );
Abc_NtkDelete( pNtkCopy );
}
if ( !Abc_NtkToSop( pNtk, 1 ) )
return;
}
else if ( FileType == IO_FILE_BENCH )
{
if ( !Abc_NtkIsStrash(pNtk) )
{
fprintf( stdout, "Writing traditional BENCH is available for AIGs only (use \"write_bench\").\n" );
return;
}
pNtkTemp = Abc_NtkToNetlistBench( pNtk );
}
else
pNtkTemp = Abc_NtkToNetlist( pNtk );
if ( pNtkTemp == NULL )
{
fprintf( stdout, "Converting to netlist has failed.\n" );
return;
}
if ( FileType == IO_FILE_BLIF )
{
if ( !Abc_NtkHasSop(pNtkTemp) && !Abc_NtkHasMapping(pNtkTemp) )
Abc_NtkToSop( pNtkTemp, 0 );
Io_WriteBlif( pNtkTemp, pFileName, 1 );
}
else if ( FileType == IO_FILE_BLIFMV )
{
if ( !Abc_NtkConvertToBlifMv( pNtkTemp ) )
return;
Io_WriteBlifMv( pNtkTemp, pFileName );
}
else if ( FileType == IO_FILE_BENCH )
Io_WriteBench( pNtkTemp, pFileName );
else if ( FileType == IO_FILE_PLA )
Io_WritePla( pNtkTemp, pFileName );
else if ( FileType == IO_FILE_EQN )
{
if ( !Abc_NtkHasAig(pNtkTemp) )
Abc_NtkToAig( pNtkTemp );
Io_WriteEqn( pNtkTemp, pFileName );
}
else if ( FileType == IO_FILE_VERILOG )
{
if ( !Abc_NtkHasAig(pNtkTemp) && !Abc_NtkHasMapping(pNtkTemp) )
Abc_NtkToAig( pNtkTemp );
Io_WriteVerilog( pNtkTemp, pFileName );
}
else
fprintf( stderr, "Unknown file format.\n" );
Abc_NtkDelete( pNtkTemp );
}
