static void
AeGenericRegisters (
void)
{
ACPI_STATUS Status;
UINT64 Value;
GenericRegister.Address = 0x1234;
GenericRegister.BitWidth = 64;
GenericRegister.BitOffset = 0;
GenericRegister.SpaceId = ACPI_ADR_SPACE_SYSTEM_IO;
Status = AcpiRead (&Value, &GenericRegister);
ACPI_CHECK_OK (AcpiRead, Status);
Status = AcpiWrite (Value, &GenericRegister);
ACPI_CHECK_OK (AcpiWrite, Status);
GenericRegister.Address = 0x12345678;
GenericRegister.BitOffset = 0;
GenericRegister.SpaceId = ACPI_ADR_SPACE_SYSTEM_MEMORY;
Status = AcpiRead (&Value, &GenericRegister);
ACPI_CHECK_OK (AcpiRead, Status);
Status = AcpiWrite (Value, &GenericRegister);
ACPI_CHECK_OK (AcpiWrite, Status);
}
static ACPI_STATUS
AcpiHwReadMultiple (
UINT32 *Value,
ACPI_GENERIC_ADDRESS *RegisterA,
ACPI_GENERIC_ADDRESS *RegisterB)
{
UINT32 ValueA = 0;
UINT32 ValueB = 0;
ACPI_STATUS Status;
/* The first register is always required */
Status = AcpiRead (&ValueA, RegisterA);
if (ACPI_FAILURE (Status))
{
return (Status);
}
/* Second register is optional */
if (RegisterB->Address)
{
Status = AcpiRead (&ValueB, RegisterB);
if (ACPI_FAILURE (Status))
{
return (Status);
}
}
/*
* OR the two return values together. No shifting or masking is necessary,
* because of how the PM1 registers are defined in the ACPI specification:
*
* "Although the bits can be split between the two register blocks (each
* register block has a unique pointer within the FADT), the bit positions
* are maintained. The register block with unimplemented bits (that is,
* those implemented in the other register block) always returns zeros,
* and writes have no side effects"
*/
*Value = (ValueA | ValueB);
return (AE_OK);
}
ACPI_STATUS
AcpiHwLowDisableGpe (
ACPI_GPE_EVENT_INFO *GpeEventInfo)
{
ACPI_GPE_REGISTER_INFO *GpeRegisterInfo;
ACPI_STATUS Status;
UINT32 EnableMask;
/* Get the info block for the entire GPE register */
GpeRegisterInfo = GpeEventInfo->RegisterInfo;
if (!GpeRegisterInfo)
{
return (AE_NOT_EXIST);
}
/* Get current value of the enable register that contains this GPE */
Status = AcpiRead (&EnableMask, &GpeRegisterInfo->EnableAddress);
if (ACPI_FAILURE (Status))
{
return (Status);
}
/* Clear just the bit that corresponds to this GPE */
ACPI_CLEAR_BIT (EnableMask, ((UINT32) 1 <<
(GpeEventInfo->GpeNumber - GpeRegisterInfo->BaseGpeNumber)));
/* Write the updated enable mask */
Status = AcpiWrite (EnableMask, &GpeRegisterInfo->EnableAddress);
return (Status);
}
ACPI_STATUS
AcpiHwExtendedSleep (
UINT8 SleepState)
{
ACPI_STATUS Status;
UINT8 SleepTypeValue;
UINT64 SleepStatus;
ACPI_FUNCTION_TRACE (HwExtendedSleep);
/* Extended sleep registers must be valid */
if (!AcpiGbl_FADT.SleepControl.Address ||
!AcpiGbl_FADT.SleepStatus.Address)
{
return_ACPI_STATUS (AE_NOT_EXIST);
}
/* Clear wake status (WAK_STS) */
Status = AcpiWrite ((UINT64) ACPI_X_WAKE_STATUS, &AcpiGbl_FADT.SleepStatus);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
AcpiGbl_SystemAwakeAndRunning = FALSE;
/* Flush caches, as per ACPI specification */
ACPI_FLUSH_CPU_CACHE ();
/*
* Set the SLP_TYP and SLP_EN bits.
*
* Note: We only use the first value returned by the \_Sx method
* (AcpiGbl_SleepTypeA) - As per ACPI specification.
*/
ACPI_DEBUG_PRINT ((ACPI_DB_INIT,
"Entering sleep state [S%u]\n", SleepState));
SleepTypeValue = ((AcpiGbl_SleepTypeA << ACPI_X_SLEEP_TYPE_POSITION) &
ACPI_X_SLEEP_TYPE_MASK);
Status = AcpiWrite ((UINT64) (SleepTypeValue | ACPI_X_SLEEP_ENABLE),
&AcpiGbl_FADT.SleepControl);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
/* Wait for transition back to Working State */
do
{
Status = AcpiRead (&SleepStatus, &AcpiGbl_FADT.SleepStatus);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
} while (!(((UINT8) SleepStatus) & ACPI_X_WAKE_STATUS));
return_ACPI_STATUS (AE_OK);
}
/*
* Idle the CPU in the lowest state possible. This function is called with
* interrupts disabled. Note that once it re-enables interrupts, a task
* switch can occur so do not access shared data (i.e. the softc) after
* interrupts are re-enabled.
*/
static void
acpi_cpu_idle()
{
struct acpi_cpu_softc *sc;
struct acpi_cx *cx_next;
uint32_t start_time, end_time;
int bm_active, cx_next_idx, i;
/* If disabled, return immediately. */
if (cpu_disable_idle) {
ACPI_ENABLE_IRQS();
return;
}
/*
* Look up our CPU id to get our softc. If it's NULL, we'll use C1
* since there is no ACPI processor object for this CPU. This occurs
* for logical CPUs in the HTT case.
*/
sc = cpu_softc[PCPU_GET(cpuid)];
if (sc == NULL) {
acpi_cpu_c1();
return;
}
/* Find the lowest state that has small enough latency. */
cx_next_idx = 0;
for (i = sc->cpu_cx_lowest; i >= 0; i--) {
if (sc->cpu_cx_states[i].trans_lat * 3 <= sc->cpu_prev_sleep) {
cx_next_idx = i;
break;
}
}
/*
* Check for bus master activity. If there was activity, clear
* the bit and use the lowest non-C3 state. Note that the USB
* driver polling for new devices keeps this bit set all the
* time if USB is loaded.
*/
if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) {
AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, &bm_active);
if (bm_active != 0) {
AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, 1);
cx_next_idx = min(cx_next_idx, sc->cpu_non_c3);
}
}
/* Select the next state and update statistics. */
cx_next = &sc->cpu_cx_states[cx_next_idx];
sc->cpu_cx_stats[cx_next_idx]++;
KASSERT(cx_next->type != ACPI_STATE_C0, ("acpi_cpu_idle: C0 sleep"));
/*
* Execute HLT (or equivalent) and wait for an interrupt. We can't
* calculate the time spent in C1 since the place we wake up is an
* ISR. Assume we slept half of quantum and return.
*/
if (cx_next->type == ACPI_STATE_C1) {
sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + 500000 / hz) / 4;
acpi_cpu_c1();
return;
}
/*
* For C3, disable bus master arbitration and enable bus master wake
* if BM control is available, otherwise flush the CPU cache.
*/
if (cx_next->type == ACPI_STATE_C3) {
if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) {
AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 1);
AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 1);
} else
ACPI_FLUSH_CPU_CACHE();
}
/*
* Read from P_LVLx to enter C2(+), checking time spent asleep.
* Use the ACPI timer for measuring sleep time. Since we need to
* get the time very close to the CPU start/stop clock logic, this
* is the only reliable time source.
*/
AcpiRead(&start_time, &AcpiGbl_FADT.XPmTimerBlock);
CPU_GET_REG(cx_next->p_lvlx, 1);
/*
* Read the end time twice. Since it may take an arbitrary time
* to enter the idle state, the first read may be executed before
* the processor has stopped. Doing it again provides enough
* margin that we are certain to have a correct value.
*/
AcpiRead(&end_time, &AcpiGbl_FADT.XPmTimerBlock);
AcpiRead(&end_time, &AcpiGbl_FADT.XPmTimerBlock);
/* Enable bus master arbitration and disable bus master wakeup. */
if (cx_next->type == ACPI_STATE_C3 &&
(cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) {
AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 0);
AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0);
}
ACPI_ENABLE_IRQS();
/* Find the actual time asleep in microseconds. */
end_time = acpi_TimerDelta(end_time, start_time);
sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + PM_USEC(end_time)) / 4;
}
ACPI_STATUS
AcpiHwGetGpeStatus (
ACPI_GPE_EVENT_INFO *GpeEventInfo,
ACPI_EVENT_STATUS *EventStatus)
{
UINT32 InByte;
UINT8 RegisterBit;
ACPI_GPE_REGISTER_INFO *GpeRegisterInfo;
ACPI_STATUS Status;
ACPI_EVENT_STATUS LocalEventStatus = 0;
ACPI_FUNCTION_ENTRY ();
if (!EventStatus)
{
return (AE_BAD_PARAMETER);
}
/* Get the info block for the entire GPE register */
GpeRegisterInfo = GpeEventInfo->RegisterInfo;
/* Get the register bitmask for this GPE */
RegisterBit = (UINT8) (1 <<
(GpeEventInfo->GpeNumber - GpeEventInfo->RegisterInfo->BaseGpeNumber));
/* GPE currently enabled? (enabled for runtime?) */
if (RegisterBit & GpeRegisterInfo->EnableForRun)
{
LocalEventStatus |= ACPI_EVENT_FLAG_ENABLED;
}
/* GPE enabled for wake? */
if (RegisterBit & GpeRegisterInfo->EnableForWake)
{
LocalEventStatus |= ACPI_EVENT_FLAG_WAKE_ENABLED;
}
/* GPE currently active (status bit == 1)? */
Status = AcpiRead (&InByte, &GpeRegisterInfo->StatusAddress);
if (ACPI_FAILURE (Status))
{
goto UnlockAndExit;
}
if (RegisterBit & InByte)
{
LocalEventStatus |= ACPI_EVENT_FLAG_SET;
}
/* Set return value */
(*EventStatus) = LocalEventStatus;
UnlockAndExit:
return (Status);
}
ACPI_STATUS
AcpiHwRegisterWrite (
UINT32 RegisterId,
UINT32 Value)
{
ACPI_STATUS Status;
UINT32 ReadValue;
ACPI_FUNCTION_TRACE (HwRegisterWrite);
switch (RegisterId)
{
case ACPI_REGISTER_PM1_STATUS: /* PM1 A/B: 16-bit access each */
/*
* Handle the "ignored" bit in PM1 Status. According to the ACPI
* specification, ignored bits are to be preserved when writing.
* Normally, this would mean a read/modify/write sequence. However,
* preserving a bit in the status register is different. Writing a
* one clears the status, and writing a zero preserves the status.
* Therefore, we must always write zero to the ignored bit.
*
* This behavior is clarified in the ACPI 4.0 specification.
*/
Value &= ~ACPI_PM1_STATUS_PRESERVED_BITS;
Status = AcpiHwWriteMultiple (Value,
&AcpiGbl_XPm1aStatus,
&AcpiGbl_XPm1bStatus);
break;
case ACPI_REGISTER_PM1_ENABLE: /* PM1 A/B: 16-bit access each */
Status = AcpiHwWriteMultiple (Value,
&AcpiGbl_XPm1aEnable,
&AcpiGbl_XPm1bEnable);
break;
case ACPI_REGISTER_PM1_CONTROL: /* PM1 A/B: 16-bit access each */
/*
* Perform a read first to preserve certain bits (per ACPI spec)
* Note: This includes SCI_EN, we never want to change this bit
*/
Status = AcpiHwReadMultiple (&ReadValue,
&AcpiGbl_FADT.XPm1aControlBlock,
&AcpiGbl_FADT.XPm1bControlBlock);
if (ACPI_FAILURE (Status))
{
goto Exit;
}
/* Insert the bits to be preserved */
ACPI_INSERT_BITS (Value, ACPI_PM1_CONTROL_PRESERVED_BITS, ReadValue);
/* Now we can write the data */
Status = AcpiHwWriteMultiple (Value,
&AcpiGbl_FADT.XPm1aControlBlock,
&AcpiGbl_FADT.XPm1bControlBlock);
break;
case ACPI_REGISTER_PM2_CONTROL: /* 8-bit access */
/*
* For control registers, all reserved bits must be preserved,
* as per the ACPI spec.
*/
Status = AcpiRead (&ReadValue, &AcpiGbl_FADT.XPm2ControlBlock);
if (ACPI_FAILURE (Status))
{
goto Exit;
}
/* Insert the bits to be preserved */
ACPI_INSERT_BITS (Value, ACPI_PM2_CONTROL_PRESERVED_BITS, ReadValue);
Status = AcpiWrite (Value, &AcpiGbl_FADT.XPm2ControlBlock);
break;
case ACPI_REGISTER_PM_TIMER: /* 32-bit access */
Status = AcpiWrite (Value, &AcpiGbl_FADT.XPmTimerBlock);
break;
case ACPI_REGISTER_SMI_COMMAND_BLOCK: /* 8-bit access */
/* SMI_CMD is currently always in IO space */
Status = AcpiHwWritePort (AcpiGbl_FADT.SmiCommand, Value, 8);
break;
default:
ACPI_ERROR ((AE_INFO, "Unknown Register ID: %X",
RegisterId));
Status = AE_BAD_PARAMETER;
break;
}
Exit:
return_ACPI_STATUS (Status);
}
ACPI_STATUS
AcpiHwRegisterRead (
UINT32 RegisterId,
UINT32 *ReturnValue)
{
UINT32 Value = 0;
ACPI_STATUS Status;
ACPI_FUNCTION_TRACE (HwRegisterRead);
switch (RegisterId)
{
case ACPI_REGISTER_PM1_STATUS: /* PM1 A/B: 16-bit access each */
Status = AcpiHwReadMultiple (&Value,
&AcpiGbl_XPm1aStatus,
&AcpiGbl_XPm1bStatus);
break;
case ACPI_REGISTER_PM1_ENABLE: /* PM1 A/B: 16-bit access each */
Status = AcpiHwReadMultiple (&Value,
&AcpiGbl_XPm1aEnable,
&AcpiGbl_XPm1bEnable);
break;
case ACPI_REGISTER_PM1_CONTROL: /* PM1 A/B: 16-bit access each */
Status = AcpiHwReadMultiple (&Value,
&AcpiGbl_FADT.XPm1aControlBlock,
&AcpiGbl_FADT.XPm1bControlBlock);
/*
* Zero the write-only bits. From the ACPI specification, "Hardware
* Write-Only Bits": "Upon reads to registers with write-only bits,
* software masks out all write-only bits."
*/
Value &= ~ACPI_PM1_CONTROL_WRITEONLY_BITS;
break;
case ACPI_REGISTER_PM2_CONTROL: /* 8-bit access */
Status = AcpiRead (&Value, &AcpiGbl_FADT.XPm2ControlBlock);
break;
case ACPI_REGISTER_PM_TIMER: /* 32-bit access */
Status = AcpiRead (&Value, &AcpiGbl_FADT.XPmTimerBlock);
break;
case ACPI_REGISTER_SMI_COMMAND_BLOCK: /* 8-bit access */
Status = AcpiHwReadPort (AcpiGbl_FADT.SmiCommand, &Value, 8);
break;
default:
ACPI_ERROR ((AE_INFO, "Unknown Register ID: %X",
RegisterId));
Status = AE_BAD_PARAMETER;
break;
}
if (ACPI_SUCCESS (Status))
{
*ReturnValue = Value;
}
return_ACPI_STATUS (Status);
}
