static void b43_phy_ht_channel_setup(struct b43_wldev *dev,
const struct b43_phy_ht_channeltab_e_phy *e,
struct ieee80211_channel *new_channel)
{
bool old_band_5ghz;
u8 i;
old_band_5ghz = b43_phy_read(dev, B43_PHY_HT_BANDCTL) & 0; /* FIXME */
if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
/* TODO */
} else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
/* TODO */
}
b43_phy_write(dev, B43_PHY_HT_BW1, e->bw1);
b43_phy_write(dev, B43_PHY_HT_BW2, e->bw2);
b43_phy_write(dev, B43_PHY_HT_BW3, e->bw3);
b43_phy_write(dev, B43_PHY_HT_BW4, e->bw4);
b43_phy_write(dev, B43_PHY_HT_BW5, e->bw5);
b43_phy_write(dev, B43_PHY_HT_BW6, e->bw6);
/* TODO: some ops on PHY regs 0x0B0 and 0xC0A */
/* TODO: separated function? */
for (i = 0; i < 3; i++) {
u16 mask;
u32 tmp = b43_httab_read(dev, B43_HTTAB32(26, 0xE8));
if (0) /* FIXME */
mask = 0x2 << (i * 4);
else
mask = 0;
b43_phy_mask(dev, B43_PHY_EXTG(0x108), mask);
b43_httab_write(dev, B43_HTTAB16(7, 0x110 + i), tmp >> 16);
b43_httab_write(dev, B43_HTTAB8(13, 0x63 + (i * 4)),
tmp & 0xFF);
b43_httab_write(dev, B43_HTTAB8(13, 0x73 + (i * 4)),
tmp & 0xFF);
}
b43_phy_write(dev, 0x017e, 0x3830);
}
static void b43_phy_ht_tx_power_fix(struct b43_wldev *dev)
{
int i;
for (i = 0; i < 3; i++) {
u16 mask;
u32 tmp = b43_httab_read(dev, B43_HTTAB32(26, 0xE8));
if (0) /* FIXME */
mask = 0x2 << (i * 4);
else
mask = 0;
b43_phy_mask(dev, B43_PHY_EXTG(0x108), mask);
b43_httab_write(dev, B43_HTTAB16(7, 0x110 + i), tmp >> 16);
b43_httab_write(dev, B43_HTTAB8(13, 0x63 + (i * 4)),
tmp & 0xFF);
b43_httab_write(dev, B43_HTTAB8(13, 0x73 + (i * 4)),
tmp & 0xFF);
}
}
static int b43_phy_ht_op_init(struct b43_wldev *dev)
{
u16 tmp;
u16 clip_state[3];
b43_phy_ht_tables_init(dev);
b43_phy_mask(dev, 0x0be, ~0x2);
b43_phy_set(dev, 0x23f, 0x7ff);
b43_phy_set(dev, 0x240, 0x7ff);
b43_phy_set(dev, 0x241, 0x7ff);
b43_phy_ht_zero_extg(dev);
b43_phy_mask(dev, B43_PHY_EXTG(0), ~0x3);
b43_phy_write(dev, B43_PHY_HT_AFE_CTL1, 0);
b43_phy_write(dev, B43_PHY_HT_AFE_CTL3, 0);
b43_phy_write(dev, B43_PHY_HT_AFE_CTL5, 0);
b43_phy_write(dev, B43_PHY_EXTG(0x103), 0x20);
b43_phy_write(dev, B43_PHY_EXTG(0x101), 0x20);
b43_phy_write(dev, 0x20d, 0xb8);
b43_phy_write(dev, B43_PHY_EXTG(0x14f), 0xc8);
b43_phy_write(dev, 0x70, 0x50);
b43_phy_write(dev, 0x1ff, 0x30);
if (0) /* TODO: condition */
; /* TODO: PHY op on reg 0x217 */
b43_phy_read(dev, 0xb0); /* TODO: what for? */
b43_phy_set(dev, 0xb0, 0x1);
b43_phy_set(dev, 0xb1, 0x91);
b43_phy_write(dev, 0x32f, 0x0003);
b43_phy_write(dev, 0x077, 0x0010);
b43_phy_write(dev, 0x0b4, 0x0258);
b43_phy_mask(dev, 0x17e, ~0x4000);
b43_phy_write(dev, 0x0b9, 0x0072);
b43_httab_write_few(dev, B43_HTTAB16(7, 0x14e), 2, 0x010f, 0x010f);
b43_httab_write_few(dev, B43_HTTAB16(7, 0x15e), 2, 0x010f, 0x010f);
b43_httab_write_few(dev, B43_HTTAB16(7, 0x16e), 2, 0x010f, 0x010f);
b43_phy_ht_afe_unk1(dev);
b43_httab_write_few(dev, B43_HTTAB16(7, 0x130), 9, 0x777, 0x111, 0x111,
0x777, 0x111, 0x111, 0x777, 0x111, 0x111);
b43_httab_write(dev, B43_HTTAB16(7, 0x120), 0x0777);
b43_httab_write(dev, B43_HTTAB16(7, 0x124), 0x0777);
b43_httab_write(dev, B43_HTTAB16(8, 0x00), 0x02);
b43_httab_write(dev, B43_HTTAB16(8, 0x10), 0x02);
b43_httab_write(dev, B43_HTTAB16(8, 0x20), 0x02);
b43_httab_write_few(dev, B43_HTTAB16(8, 0x08), 4,
0x8e, 0x96, 0x96, 0x96);
b43_httab_write_few(dev, B43_HTTAB16(8, 0x18), 4,
0x8f, 0x9f, 0x9f, 0x9f);
b43_httab_write_few(dev, B43_HTTAB16(8, 0x28), 4,
0x8f, 0x9f, 0x9f, 0x9f);
b43_httab_write_few(dev, B43_HTTAB16(8, 0x0c), 4, 0x2, 0x2, 0x2, 0x2);
b43_httab_write_few(dev, B43_HTTAB16(8, 0x1c), 4, 0x2, 0x2, 0x2, 0x2);
b43_httab_write_few(dev, B43_HTTAB16(8, 0x2c), 4, 0x2, 0x2, 0x2, 0x2);
b43_phy_maskset(dev, 0x0280, 0xff00, 0x3e);
b43_phy_maskset(dev, 0x0283, 0xff00, 0x3e);
b43_phy_maskset(dev, B43_PHY_OFDM(0x0141), 0xff00, 0x46);
b43_phy_maskset(dev, 0x0283, 0xff00, 0x40);
b43_httab_write_few(dev, B43_HTTAB16(00, 0x8), 4,
0x09, 0x0e, 0x13, 0x18);
b43_httab_write_few(dev, B43_HTTAB16(01, 0x8), 4,
0x09, 0x0e, 0x13, 0x18);
/* TODO: Did wl mean 2 instead of 40? */
b43_httab_write_few(dev, B43_HTTAB16(40, 0x8), 4,
0x09, 0x0e, 0x13, 0x18);
b43_phy_maskset(dev, B43_PHY_OFDM(0x24), 0x3f, 0xd);
b43_phy_maskset(dev, B43_PHY_OFDM(0x64), 0x3f, 0xd);
b43_phy_maskset(dev, B43_PHY_OFDM(0xa4), 0x3f, 0xd);
b43_phy_set(dev, B43_PHY_EXTG(0x060), 0x1);
b43_phy_set(dev, B43_PHY_EXTG(0x064), 0x1);
b43_phy_set(dev, B43_PHY_EXTG(0x080), 0x1);
b43_phy_set(dev, B43_PHY_EXTG(0x084), 0x1);
/* Copy some tables entries */
tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x144));
b43_httab_write(dev, B43_HTTAB16(7, 0x14a), tmp);
tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x154));
b43_httab_write(dev, B43_HTTAB16(7, 0x15a), tmp);
tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x164));
b43_httab_write(dev, B43_HTTAB16(7, 0x16a), tmp);
/* Reset CCA */
b43_phy_force_clock(dev, true);
tmp = b43_phy_read(dev, B43_PHY_HT_BBCFG);
b43_phy_write(dev, B43_PHY_HT_BBCFG, tmp | B43_PHY_HT_BBCFG_RSTCCA);
b43_phy_write(dev, B43_PHY_HT_BBCFG, tmp & ~B43_PHY_HT_BBCFG_RSTCCA);
b43_phy_force_clock(dev, false);
b43_mac_phy_clock_set(dev, true);
b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RX2TX);
b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RST2RX);
/* TODO: PHY op on reg 0xb0 */
/* TODO: Should we restore it? Or store it in global PHY info? */
b43_phy_ht_read_clip_detection(dev, clip_state);
if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
b43_phy_ht_bphy_init(dev);
b43_httab_write_bulk(dev, B43_HTTAB32(0x1a, 0xc0),
B43_HTTAB_1A_C0_LATE_SIZE, b43_httab_0x1a_0xc0_late);
return 0;
}
static void lo_measure_restore(struct b43_wldev *dev,
struct lo_g_saved_values *sav)
{
struct b43_phy *phy = &dev->phy;
struct b43_txpower_lo_control *lo = phy->lo_control;
u16 tmp;
if (phy->rev >= 2) {
b43_phy_write(dev, B43_PHY_PGACTL, 0xE300);
tmp = (phy->pga_gain << 8);
b43_phy_write(dev, B43_PHY_RFOVERVAL, tmp | 0xA0);
udelay(5);
b43_phy_write(dev, B43_PHY_RFOVERVAL, tmp | 0xA2);
udelay(2);
b43_phy_write(dev, B43_PHY_RFOVERVAL, tmp | 0xA3);
} else {
tmp = (phy->pga_gain | 0xEFA0);
b43_phy_write(dev, B43_PHY_PGACTL, tmp);
}
if (b43_has_hardware_pctl(phy)) {
b43_gphy_dc_lt_init(dev);
} else {
if (lo->rebuild)
b43_lo_g_adjust_to(dev, 3, 2, 0);
else
b43_lo_g_adjust(dev);
}
if (phy->type == B43_PHYTYPE_G) {
if (phy->rev >= 3)
b43_phy_write(dev, B43_PHY_CCK(0x2E), 0xC078);
else
b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x8078);
if (phy->rev >= 2)
b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x0202);
else
b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x0101);
}
b43_write16(dev, 0x3F4, sav->reg_3F4);
b43_phy_write(dev, B43_PHY_PGACTL, sav->phy_pgactl);
b43_phy_write(dev, B43_PHY_CCK(0x2A), sav->phy_cck_2A);
b43_phy_write(dev, B43_PHY_SYNCCTL, sav->phy_syncctl);
b43_phy_write(dev, B43_PHY_DACCTL, sav->phy_dacctl);
b43_radio_write16(dev, 0x43, sav->radio_43);
b43_radio_write16(dev, 0x7A, sav->radio_7A);
if (!has_tx_magnification(phy)) {
tmp = sav->radio_52;
b43_radio_write16(dev, 0x52, (b43_radio_read16(dev, 0x52)
& 0xFF0F) | tmp);
}
b43_write16(dev, 0x3E2, sav->reg_3E2);
if (phy->type == B43_PHYTYPE_B &&
phy->radio_ver == 0x2050 && phy->radio_rev <= 5) {
b43_phy_write(dev, B43_PHY_CCK(0x30), sav->phy_cck_30);
b43_phy_write(dev, B43_PHY_CCK(0x06), sav->phy_cck_06);
}
if (phy->rev >= 2) {
b43_phy_write(dev, B43_PHY_ANALOGOVER, sav->phy_analogover);
b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
sav->phy_analogoverval);
b43_phy_write(dev, B43_PHY_CLASSCTL, sav->phy_classctl);
b43_phy_write(dev, B43_PHY_RFOVER, sav->phy_rfover);
b43_phy_write(dev, B43_PHY_RFOVERVAL, sav->phy_rfoverval);
b43_phy_write(dev, B43_PHY_CCK(0x3E), sav->phy_cck_3E);
b43_phy_write(dev, B43_PHY_CRS0, sav->phy_crs0);
}
if (b43_has_hardware_pctl(phy)) {
tmp = (sav->phy_lo_mask & 0xBFFF);
b43_phy_write(dev, B43_PHY_LO_MASK, tmp);
b43_phy_write(dev, B43_PHY_EXTG(0x01), sav->phy_extg_01);
b43_phy_write(dev, B43_PHY_DACCTL, sav->phy_dacctl_hwpctl);
b43_phy_write(dev, B43_PHY_CCK(0x14), sav->phy_cck_14);
b43_phy_write(dev, B43_PHY_HPWR_TSSICTL, sav->phy_hpwr_tssictl);
}
b43_radio_selectchannel(dev, sav->old_channel, 1);
}
static void lo_measure_setup(struct b43_wldev *dev,
struct lo_g_saved_values *sav)
{
struct ssb_sprom *sprom = &dev->dev->bus->sprom;
struct b43_phy *phy = &dev->phy;
struct b43_txpower_lo_control *lo = phy->lo_control;
u16 tmp;
if (b43_has_hardware_pctl(phy)) {
sav->phy_lo_mask = b43_phy_read(dev, B43_PHY_LO_MASK);
sav->phy_extg_01 = b43_phy_read(dev, B43_PHY_EXTG(0x01));
sav->phy_dacctl_hwpctl = b43_phy_read(dev, B43_PHY_DACCTL);
sav->phy_cck_14 = b43_phy_read(dev, B43_PHY_CCK(0x14));
sav->phy_hpwr_tssictl = b43_phy_read(dev, B43_PHY_HPWR_TSSICTL);
b43_phy_write(dev, B43_PHY_HPWR_TSSICTL,
b43_phy_read(dev, B43_PHY_HPWR_TSSICTL)
| 0x100);
b43_phy_write(dev, B43_PHY_EXTG(0x01),
b43_phy_read(dev, B43_PHY_EXTG(0x01))
| 0x40);
b43_phy_write(dev, B43_PHY_DACCTL,
b43_phy_read(dev, B43_PHY_DACCTL)
| 0x40);
b43_phy_write(dev, B43_PHY_CCK(0x14),
b43_phy_read(dev, B43_PHY_CCK(0x14))
| 0x200);
}
if (phy->type == B43_PHYTYPE_B &&
phy->radio_ver == 0x2050 && phy->radio_rev < 6) {
b43_phy_write(dev, B43_PHY_CCK(0x16), 0x410);
b43_phy_write(dev, B43_PHY_CCK(0x17), 0x820);
}
if (!lo->rebuild && b43_has_hardware_pctl(phy))
lo_read_power_vector(dev);
if (phy->rev >= 2) {
sav->phy_analogover = b43_phy_read(dev, B43_PHY_ANALOGOVER);
sav->phy_analogoverval =
b43_phy_read(dev, B43_PHY_ANALOGOVERVAL);
sav->phy_rfover = b43_phy_read(dev, B43_PHY_RFOVER);
sav->phy_rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL);
sav->phy_classctl = b43_phy_read(dev, B43_PHY_CLASSCTL);
sav->phy_cck_3E = b43_phy_read(dev, B43_PHY_CCK(0x3E));
sav->phy_crs0 = b43_phy_read(dev, B43_PHY_CRS0);
b43_phy_write(dev, B43_PHY_CLASSCTL,
b43_phy_read(dev, B43_PHY_CLASSCTL)
& 0xFFFC);
b43_phy_write(dev, B43_PHY_CRS0, b43_phy_read(dev, B43_PHY_CRS0)
& 0x7FFF);
b43_phy_write(dev, B43_PHY_ANALOGOVER,
b43_phy_read(dev, B43_PHY_ANALOGOVER)
| 0x0003);
b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
b43_phy_read(dev, B43_PHY_ANALOGOVERVAL)
& 0xFFFC);
if (phy->type == B43_PHYTYPE_G) {
if ((phy->rev >= 7) &&
(sprom->boardflags_lo & B43_BFL_EXTLNA)) {
b43_phy_write(dev, B43_PHY_RFOVER, 0x933);
} else {
b43_phy_write(dev, B43_PHY_RFOVER, 0x133);
}
} else {
b43_phy_write(dev, B43_PHY_RFOVER, 0);
}
b43_phy_write(dev, B43_PHY_CCK(0x3E), 0);
}
sav->reg_3F4 = b43_read16(dev, 0x3F4);
sav->reg_3E2 = b43_read16(dev, 0x3E2);
sav->radio_43 = b43_radio_read16(dev, 0x43);
sav->radio_7A = b43_radio_read16(dev, 0x7A);
sav->phy_pgactl = b43_phy_read(dev, B43_PHY_PGACTL);
sav->phy_cck_2A = b43_phy_read(dev, B43_PHY_CCK(0x2A));
sav->phy_syncctl = b43_phy_read(dev, B43_PHY_SYNCCTL);
sav->phy_dacctl = b43_phy_read(dev, B43_PHY_DACCTL);
if (!has_tx_magnification(phy)) {
sav->radio_52 = b43_radio_read16(dev, 0x52);
sav->radio_52 &= 0x00F0;
}
if (phy->type == B43_PHYTYPE_B) {
sav->phy_cck_30 = b43_phy_read(dev, B43_PHY_CCK(0x30));
sav->phy_cck_06 = b43_phy_read(dev, B43_PHY_CCK(0x06));
b43_phy_write(dev, B43_PHY_CCK(0x30), 0x00FF);
b43_phy_write(dev, B43_PHY_CCK(0x06), 0x3F3F);
} else {
b43_write16(dev, 0x3E2, b43_read16(dev, 0x3E2)
| 0x8000);
}
b43_write16(dev, 0x3F4, b43_read16(dev, 0x3F4)
& 0xF000);
tmp =
(phy->type == B43_PHYTYPE_G) ? B43_PHY_LO_MASK : B43_PHY_CCK(0x2E);
b43_phy_write(dev, tmp, 0x007F);
tmp = sav->phy_syncctl;
b43_phy_write(dev, B43_PHY_SYNCCTL, tmp & 0xFF7F);
tmp = sav->radio_7A;
b43_radio_write16(dev, 0x007A, tmp & 0xFFF0);
b43_phy_write(dev, B43_PHY_CCK(0x2A), 0x8A3);
if (phy->type == B43_PHYTYPE_G ||
(phy->type == B43_PHYTYPE_B &&
phy->radio_ver == 0x2050 && phy->radio_rev >= 6)) {
b43_phy_write(dev, B43_PHY_CCK(0x2B), 0x1003);
} else
b43_phy_write(dev, B43_PHY_CCK(0x2B), 0x0802);
if (phy->rev >= 2)
b43_dummy_transmission(dev);
b43_radio_selectchannel(dev, 6, 0);
b43_radio_read16(dev, 0x51); /* dummy read */
if (phy->type == B43_PHYTYPE_G)
b43_phy_write(dev, B43_PHY_CCK(0x2F), 0);
if (lo->rebuild)
lo_measure_txctl_values(dev);
if (phy->type == B43_PHYTYPE_G && phy->rev >= 3) {
b43_phy_write(dev, B43_PHY_LO_MASK, 0xC078);
} else {
if (phy->type == B43_PHYTYPE_B)
b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x8078);
else
b43_phy_write(dev, B43_PHY_LO_MASK, 0x8078);
}
}
static int b43_phy_ht_op_init(struct b43_wldev *dev)
{
struct b43_phy_ht *phy_ht = dev->phy.ht;
u16 tmp;
u16 clip_state[3];
bool saved_tx_pwr_ctl;
if (dev->dev->bus_type != B43_BUS_BCMA) {
b43err(dev->wl, "HT-PHY is supported only on BCMA bus!\n");
return -EOPNOTSUPP;
}
b43_phy_ht_tables_init(dev);
b43_phy_mask(dev, 0x0be, ~0x2);
b43_phy_set(dev, 0x23f, 0x7ff);
b43_phy_set(dev, 0x240, 0x7ff);
b43_phy_set(dev, 0x241, 0x7ff);
b43_phy_ht_zero_extg(dev);
b43_phy_mask(dev, B43_PHY_EXTG(0), ~0x3);
b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0);
b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0);
b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0);
b43_phy_write(dev, B43_PHY_EXTG(0x103), 0x20);
b43_phy_write(dev, B43_PHY_EXTG(0x101), 0x20);
b43_phy_write(dev, 0x20d, 0xb8);
b43_phy_write(dev, B43_PHY_EXTG(0x14f), 0xc8);
b43_phy_write(dev, 0x70, 0x50);
b43_phy_write(dev, 0x1ff, 0x30);
if (0) /* TODO: condition */
; /* TODO: PHY op on reg 0x217 */
if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_CCK_EN, 0);
else
b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_CCK_EN,
B43_PHY_HT_CLASS_CTL_CCK_EN);
b43_phy_set(dev, 0xb1, 0x91);
b43_phy_write(dev, 0x32f, 0x0003);
b43_phy_write(dev, 0x077, 0x0010);
b43_phy_write(dev, 0x0b4, 0x0258);
b43_phy_mask(dev, 0x17e, ~0x4000);
b43_phy_write(dev, 0x0b9, 0x0072);
b43_httab_write_few(dev, B43_HTTAB16(7, 0x14e), 2, 0x010f, 0x010f);
b43_httab_write_few(dev, B43_HTTAB16(7, 0x15e), 2, 0x010f, 0x010f);
b43_httab_write_few(dev, B43_HTTAB16(7, 0x16e), 2, 0x010f, 0x010f);
b43_phy_ht_afe_unk1(dev);
b43_httab_write_few(dev, B43_HTTAB16(7, 0x130), 9, 0x777, 0x111, 0x111,
0x777, 0x111, 0x111, 0x777, 0x111, 0x111);
b43_httab_write(dev, B43_HTTAB16(7, 0x120), 0x0777);
b43_httab_write(dev, B43_HTTAB16(7, 0x124), 0x0777);
b43_httab_write(dev, B43_HTTAB16(8, 0x00), 0x02);
b43_httab_write(dev, B43_HTTAB16(8, 0x10), 0x02);
b43_httab_write(dev, B43_HTTAB16(8, 0x20), 0x02);
b43_httab_write_few(dev, B43_HTTAB16(8, 0x08), 4,
0x8e, 0x96, 0x96, 0x96);
b43_httab_write_few(dev, B43_HTTAB16(8, 0x18), 4,
0x8f, 0x9f, 0x9f, 0x9f);
b43_httab_write_few(dev, B43_HTTAB16(8, 0x28), 4,
0x8f, 0x9f, 0x9f, 0x9f);
b43_httab_write_few(dev, B43_HTTAB16(8, 0x0c), 4, 0x2, 0x2, 0x2, 0x2);
b43_httab_write_few(dev, B43_HTTAB16(8, 0x1c), 4, 0x2, 0x2, 0x2, 0x2);
b43_httab_write_few(dev, B43_HTTAB16(8, 0x2c), 4, 0x2, 0x2, 0x2, 0x2);
b43_phy_maskset(dev, 0x0280, 0xff00, 0x3e);
b43_phy_maskset(dev, 0x0283, 0xff00, 0x3e);
b43_phy_maskset(dev, B43_PHY_OFDM(0x0141), 0xff00, 0x46);
b43_phy_maskset(dev, 0x0283, 0xff00, 0x40);
b43_httab_write_few(dev, B43_HTTAB16(00, 0x8), 4,
0x09, 0x0e, 0x13, 0x18);
b43_httab_write_few(dev, B43_HTTAB16(01, 0x8), 4,
0x09, 0x0e, 0x13, 0x18);
/* TODO: Did wl mean 2 instead of 40? */
b43_httab_write_few(dev, B43_HTTAB16(40, 0x8), 4,
0x09, 0x0e, 0x13, 0x18);
b43_phy_maskset(dev, B43_PHY_OFDM(0x24), 0x3f, 0xd);
b43_phy_maskset(dev, B43_PHY_OFDM(0x64), 0x3f, 0xd);
b43_phy_maskset(dev, B43_PHY_OFDM(0xa4), 0x3f, 0xd);
b43_phy_set(dev, B43_PHY_EXTG(0x060), 0x1);
b43_phy_set(dev, B43_PHY_EXTG(0x064), 0x1);
b43_phy_set(dev, B43_PHY_EXTG(0x080), 0x1);
b43_phy_set(dev, B43_PHY_EXTG(0x084), 0x1);
/* Copy some tables entries */
tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x144));
b43_httab_write(dev, B43_HTTAB16(7, 0x14a), tmp);
tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x154));
b43_httab_write(dev, B43_HTTAB16(7, 0x15a), tmp);
tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x164));
b43_httab_write(dev, B43_HTTAB16(7, 0x16a), tmp);
/* Reset CCA */
b43_phy_force_clock(dev, true);
tmp = b43_phy_read(dev, B43_PHY_HT_BBCFG);
b43_phy_write(dev, B43_PHY_HT_BBCFG, tmp | B43_PHY_HT_BBCFG_RSTCCA);
b43_phy_write(dev, B43_PHY_HT_BBCFG, tmp & ~B43_PHY_HT_BBCFG_RSTCCA);
b43_phy_force_clock(dev, false);
b43_mac_phy_clock_set(dev, true);
b43_phy_ht_pa_override(dev, false);
b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RX2TX);
b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RST2RX);
b43_phy_ht_pa_override(dev, true);
/* TODO: Should we restore it? Or store it in global PHY info? */
b43_phy_ht_classifier(dev, 0, 0);
b43_phy_ht_read_clip_detection(dev, clip_state);
if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
b43_phy_ht_bphy_init(dev);
b43_httab_write_bulk(dev, B43_HTTAB32(0x1a, 0xc0),
B43_HTTAB_1A_C0_LATE_SIZE, b43_httab_0x1a_0xc0_late);
saved_tx_pwr_ctl = phy_ht->tx_pwr_ctl;
b43_phy_ht_tx_power_fix(dev);
b43_phy_ht_tx_power_ctl(dev, false);
b43_phy_ht_tx_power_ctl_idle_tssi(dev);
b43_phy_ht_tx_power_ctl_setup(dev);
b43_phy_ht_tx_power_ctl(dev, saved_tx_pwr_ctl);
return 0;
}
