static u32 lradc_get_ch_value (int channel)
{
u32 channel_mask = (1 << channel);
/* Clear the interrupt flag */
HW_LRADC_CTRL1_CLR(channel_mask);
/* Kick of a conversion */
HW_LRADC_CTRL0_SET(BF_LRADC_CTRL0_SCHEDULE(channel_mask));
/* wait for completion */
while ((HW_LRADC_CTRL1_RD() & channel_mask) != channel_mask) ;
/* Clear the interrupt flag */
HW_LRADC_CTRL1_CLR(channel_mask);
/* read ch 6 value. */
return HW_LRADC_CHn_RD(channel) & BM_LRADC_CHn_VALUE;
}
u32 hw_lradc_vddio(void)
{
/* Clear the Soft Reset and Clock Gate for normal operation */
__raw_writel(BM_LRADC_CTRL0_SFTRST | BM_LRADC_CTRL0_CLKGATE,
mxs_lradc.base + HW_LRADC_CTRL0_CLR);
/*
* Clear the divide by two for channel 6 since
* it has a HW divide-by-two built in.
*/
__raw_writel(BF_LRADC_CTRL2_DIVIDE_BY_TWO(1 << VDDIO_VOLTAGE_CH),
mxs_lradc.base + HW_LRADC_CTRL2_CLR);
/* Clear the accumulator & NUM_SAMPLES */
__raw_writel(0xFFFFFFFF,
mxs_lradc.base + HW_LRADC_CHn_CLR(VDDIO_VOLTAGE_CH));
/* Clear the interrupt flag */
__raw_writel(BM_LRADC_CTRL1_LRADC6_IRQ,
mxs_lradc.base + HW_LRADC_CTRL1_CLR);
/*
* Get VddIO; this is the max scale value for the button resistor
* ladder.
* schedule ch 6:
*/
__raw_writel(BF_LRADC_CTRL0_SCHEDULE(1 << VDDIO_VOLTAGE_CH),
mxs_lradc.base + HW_LRADC_CTRL0_SET);
/* wait for completion */
while ((__raw_readl(mxs_lradc.base + HW_LRADC_CTRL1)
& BM_LRADC_CTRL1_LRADC6_IRQ) != BM_LRADC_CTRL1_LRADC6_IRQ)
cpu_relax();
/* Clear the interrupt flag */
__raw_writel(BM_LRADC_CTRL1_LRADC6_IRQ,
mxs_lradc.base + HW_LRADC_CTRL1_CLR);
/* read ch 6 value. */
return __raw_readl(mxs_lradc.base + HW_LRADC_CHn(VDDIO_VOLTAGE_CH)) &
BM_LRADC_CHn_VALUE;
}