void Timer32_initModule(uint32_t timer, uint32_t preScaler, uint32_t resolution,
uint32_t mode)
{
/* Setting up one shot or continuous mode */
if (mode == TIMER32_PERIODIC_MODE)
BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_MODE_OFS)
= 1;
else if (mode == TIMER32_FREE_RUN_MODE)
BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_MODE_OFS)
= 0;
else
ASSERT(false);
/* Setting the resolution of the timer */
if (resolution == TIMER32_1_MODULE6BIT)
BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_SIZE_OFS)
= 0;
else if (resolution == TIMER32_32BIT)
BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_SIZE_OFS)
= 1;
else
ASSERT(false);
/* Setting the PreScaler */
ASSERT(
resolution == TIMER32_PRESCALER_1
|| resolution == TIMER32_PRESCALER_16
|| resolution == TIMER32_PRESCALER_256);
TIMER32_CMSIS(timer)->CONTROL = TIMER32_CMSIS(timer)->CONTROL
& (~TIMER32_CONTROL_PRESCALE_MASK) | preScaler;
}
bool I2C_masterReceiveMultiByteFinishWithTimeout(uint32_t moduleInstance,
uint8_t *txData, uint32_t timeout)
{
uint32_t timeout2 = timeout;
ASSERT(timeout > 0);
//Send stop condition.
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTXSTP_OFS) = 1;
//Wait for Stop to finish
while (BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r, UCTXSTP_OFS)
&& --timeout)
;
//Check if transfer timed out
if (timeout == 0)
return false;
// Wait for RX buffer
while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCRXIFG_OFS))
&& --timeout2)
;
//Check if transfer timed out
if (timeout2 == 0)
return false;
//Capture data from receive buffer after setting stop bit due to
//MSP430 I2C critical timing.
*txData = (EUSCI_B_CMSIS(moduleInstance)->rRXBUF.b.bRXBUF);
return true;
}
void Timer_A_configureUpDownMode(uint32_t timer,
const Timer_A_UpDownModeConfig *config)
{
ASSERT(
(TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK == config->clockSource)
|| (TIMER_A_CLOCKSOURCE_ACLK == config->clockSource)
|| (TIMER_A_CLOCKSOURCE_SMCLK == config->clockSource)
|| (TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK
== config->clockSource));
ASSERT(
(TIMER_A_DO_CLEAR == config->timerClear)
|| (TIMER_A_SKIP_CLEAR == config->timerClear));
ASSERT(
(TIMER_A_DO_CLEAR == config->timerClear)
|| (TIMER_A_SKIP_CLEAR == config->timerClear));
privateTimer_AProcessClockSourceDivider(timer, config->clockSourceDivider);
TIMER_A_CMSIS(timer)->rCTL.r &=
~(TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + TIMER_A_UPDOWN_MODE
+ TIMER_A_DO_CLEAR + TIMER_A_TAIE_INTERRUPT_ENABLE);
TIMER_A_CMSIS(timer)->rCTL.r |= (config->clockSource + TIMER_A_STOP_MODE
+ config->timerClear + config->timerInterruptEnable_TAIE);
if (TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE
== config->captureCompareInterruptEnable_CCR0_CCIE)
BITBAND_PERI(TIMER_A_CMSIS(timer)->rCCTL0.r,CCIE_OFS) = 1;
else
BITBAND_PERI(TIMER_A_CMSIS(timer)->rCCTL0.r,CCIE_OFS) = 0;
TIMER_A_CMSIS(timer)->rCCR0 = config->timerPeriod;
}
bool I2C_masterSendMultiByteStartWithTimeout(uint32_t moduleInstance,
uint8_t txData, uint32_t timeout)
{
uint16_t txieStatus;
ASSERT(timeout > 0);
//Store current transmit interrupt enable
txieStatus = EUSCI_B_CMSIS(moduleInstance)->rIE.r & UCTXIE;
//Disable transmit interrupt enable
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r,UCTXIE_OFS) = 0;
//Send start condition.
EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r |= UCTR + UCTXSTT;
//Poll for transmit interrupt flag.
while ((!(BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
&& --timeout))
;
//Check if transfer timed out
if (timeout == 0)
return false;
//Send single byte data.
EUSCI_B_CMSIS(moduleInstance)->rTXBUF.r = txData;
//Reinstate transmit interrupt enable
EUSCI_B_CMSIS(moduleInstance)->rIE.r |= txieStatus;
return true;
}
uint_fast8_t RTC_C_getInterruptStatus(void)
{
uint_fast8_t tempInterruptFlagMask = 0x00;
uint_fast8_t interruptFlagMask = RTC_C_TIME_EVENT_INTERRUPT
| RTC_C_CLOCK_ALARM_INTERRUPT | RTC_C_CLOCK_READ_READY_INTERRUPT
| RTC_C_PRESCALE_TIMER0_INTERRUPT | RTC_C_PRESCALE_TIMER1_INTERRUPT
| RTC_C_OSCILLATOR_FAULT_INTERRUPT;
tempInterruptFlagMask |= (RTC_C->rCTL0.r & (interruptFlagMask >> 4));
tempInterruptFlagMask = tempInterruptFlagMask << 4;
if (interruptFlagMask & RTC_C_PRESCALE_TIMER0_INTERRUPT)
{
if (BITBAND_PERI(RTC_C->rPS0CTL.r, RT0PSIFG_OFS))
{
tempInterruptFlagMask |= RTC_C_PRESCALE_TIMER0_INTERRUPT;
}
}
if (interruptFlagMask & RTC_C_PRESCALE_TIMER1_INTERRUPT)
{
if (BITBAND_PERI(RTC_C->rPS1CTL.r, RT1PSIFG_OFS))
{
tempInterruptFlagMask |= RTC_C_PRESCALE_TIMER1_INTERRUPT;
}
}
return (tempInterruptFlagMask);
}
void UART_transmitData(uint32_t moduleInstance, uint_fast8_t transmitData)
{
/* If interrupts are not used, poll for flags */
if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IE, EUSCI_A__TXIE_OFS))
while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IFG, EUSCI_A_IFG_TXIFG_OFS))
;
EUSCI_A_CMSIS(moduleInstance)->TXBUF = transmitData;
}
uint8_t UART_receiveData(uint32_t moduleInstance)
{
/* If interrupts are not used, poll for flags */
if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IE, EUSCI_A__RXIE_OFS))
while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IFG, EUSCI_A_IFG_RXIFG_OFS))
;
return EUSCI_A_CMSIS(moduleInstance)->RXBUF;
}
void CS_disableDCOExternalResistor(void)
{
/* Unlocking the module */
CS->rKEY.r = CS_KEY;
BITBAND_PERI(CS->rCTL0.r,DCORES_OFS) = 0;
/* Locking the module */
BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
}
void CS_disableDCOExternalResistor(void)
{
/* Unlocking the module */
CS->KEY = CS_KEY;
BITBAND_PERI(CS->CTL0,CS_CTL0_DCORES_OFS) = 0;
/* Locking the module */
BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
}
bool COMP_E_initModule(uint32_t comparator, const COMP_E_Config *config)
{
uint_fast8_t positiveTerminalInput = __getRegisterSettingForInput(
config->positiveTerminalInput);
uint_fast8_t negativeTerminalInput = __getRegisterSettingForInput(
config->negativeTerminalInput);
bool retVal = true;
ASSERT(positiveTerminalInput < 0x10); ASSERT(negativeTerminalInput < 0x10);
ASSERT(positiveTerminalInput != negativeTerminalInput);
ASSERT(
config->outputFilterEnableAndDelayLevel
<= COMP_E_FILTEROUTPUT_DLYLVL4);
/* Reset COMPE Control 1 & Interrupt Registers for initialization */
COMP_E_CMSIS(comparator)->CTL0 = 0;
COMP_E_CMSIS(comparator)->INT = 0;
// Set the Positive Terminal
if (COMP_E_VREF != positiveTerminalInput)
{
// Enable Positive Terminal Input Mux and Set to the appropriate input
COMP_E_CMSIS(comparator)->CTL0 |= COMP_E_CTL0_IPEN
+ positiveTerminalInput;
// Disable the input buffer
COMP_E_CMSIS(comparator)->CTL3 |= (1 << positiveTerminalInput);
} else
{
// Reset and Set COMPE Control 2 Register
BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL2,COMP_E_CTL2_RSEL_OFS) = 0;
}
// Set the Negative Terminal
if (COMP_E_VREF != negativeTerminalInput)
{
// Enable Negative Terminal Input Mux and Set to the appropriate input
COMP_E_CMSIS(comparator)->CTL0 |= COMP_E_CTL0_IMEN
+ (negativeTerminalInput << 8);
// Disable the input buffer
COMP_E_CMSIS(comparator)->CTL3 |= (1 << negativeTerminalInput);
} else
{
// Reset and Set COMPE Control 2 Register
BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL2, COMP_E_CTL2_RSEL_OFS) = 1;
}
// Reset and Set COMPE Control 1 Register
COMP_E_CMSIS(comparator)->CTL1 = config->powerMode
+ config->outputFilterEnableAndDelayLevel
+ config->invertedOutputPolarity;
return retVal;
}
bool CS_startHFXTWithTimeout(bool bypassMode, uint32_t timeout)
{
uint32_t wHFFreqRange;
uint_fast8_t bNMIStatus;
bool boolTimeout;
/* Unlocking the CS Module */
CS->KEY = CS_KEY;
/* Saving status and temporarily disabling NMIs for UCS faults */
bNMIStatus = SysCtl_getNMISourceStatus() & SYSCTL_CS_SRC;
SysCtl_disableNMISource(SYSCTL_CS_SRC);
/* Determining which frequency range to use */
wHFFreqRange = _CSGetHFXTFrequency();
boolTimeout = (timeout == 0) ? false : true;
/* Setting to maximum drive strength */
BITBAND_PERI(CS->CTL2, CS_CTL2_HFXTDRIVE_OFS) = 1;
CS->CTL2 = (CS->CTL2 & (~CS_CTL2_HFXTFREQ_MASK)) | (wHFFreqRange);
if (bypassMode)
{
BITBAND_PERI(CS->CTL2, CS_CTL2_HFXTBYPASS_OFS) = 1;
} else
{
BITBAND_PERI(CS->CTL2, CS_CTL2_HFXTBYPASS_OFS) = 0;
}
/* Starting and Waiting for frequency stabilization */
BITBAND_PERI(CS->CTL2, CS_CTL2_HFXT_EN_OFS) = 1;
while (BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
{
if (boolTimeout && ((--timeout) == 0))
break;
BITBAND_PERI(CS->CLRIFG,CS_CLRIFG_CLR_HFXTIFG_OFS) = 1;
}
/* Setting the drive strength */
if (!bypassMode)
{
if (wHFFreqRange != CS_CTL2_HFXTFREQ_0)
BITBAND_PERI(CS->CTL2, CS_CTL2_HFXTDRIVE_OFS) = 1;
else
BITBAND_PERI(CS->CTL2, CS_CTL2_HFXTDRIVE_OFS) = 0;
}
/* Locking the module */
BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
/* Enabling the NMI state */
SysCtl_enableNMISource(bNMIStatus);
if(boolTimeout && timeout == 0)
return false;
return true;
}
void PSS_setHighSidePerformanceMode(uint_fast8_t powerMode)
{
__PSSUnlock();
if (powerMode == PSS_FULL_PERFORMANCE_MODE)
BITBAND_PERI(PSS->rCTL0.r, SVSMHLP_OFS) = 0;
else
BITBAND_PERI(PSS->rCTL0.r, SVSMHLP_OFS) = 1;
__PSSLock();
}
void COMP_E_setInterruptEdgeDirection(uint32_t comparator,
uint_fast8_t edgeDirection)
{
ASSERT(edgeDirection <= COMP_E_RISINGEDGE);
// Set the edge direction that will trigger an interrupt
if (COMP_E_RISINGEDGE == edgeDirection)
BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL1.r, CEIES_OFS) = 1;
else if (COMP_E_FALLINGEDGE == edgeDirection)
BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL1.r, CEIES_OFS) = 0;
}
//*****************************************************************************
//
//! \brief Initializes the SPI Master clock. At the end of this function call,
//! SPI module is left enabled.
//!
//! \param baseAddress is the base address of the EUSCI_A_SPI module.
//! \param clockSourceFrequency is the frequency of the slected clock source
//! \param desiredSpiClock is the desired clock rate for SPI communication
//!
//! Modified bits are \b UCSWRST of \b UCAxCTLW0 register.
//!
//! \return None
//
//*****************************************************************************
void EUSCI_A_SPI_masterChangeClock(uint32_t baseAddress,
uint32_t clockSourceFrequency, uint32_t desiredSpiClock)
{
//Disable the USCI Module
BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
EUSCI_A_CMSIS(baseAddress)->rBRW = (uint16_t) (clockSourceFrequency
/ desiredSpiClock);
//Reset the UCSWRST bit to enable the USCI Module
BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 0;
}
uint8_t I2C_masterReceiveSingle(uint32_t moduleInstance)
{
//Polling RXIFG0 if RXIE is not enabled
if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r, UCRXIE0_OFS))
{
while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r,
UCRXIFG0_OFS))
;
}
//Read a byte.
return EUSCI_B_CMSIS(moduleInstance)->rRXBUF.b.bRXBUF;
}
void Timer32_startTimer(uint32_t timer, bool oneShot)
{
ASSERT(timer == TIMER32_0_MODULE || timer == TIMER32_1_MODULE);
if (oneShot)
BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_ONESHOT_OFS)
= 1;
else
BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_ONESHOT_OFS)
= 0;
TIMER32_CMSIS(timer)->CONTROL |= TIMER32_CONTROL_ENABLE;
}
bool RTC_C_setTemperatureCompensation(uint_fast16_t offsetDirection,
uint_fast8_t offsetValue)
{
while (!BITBAND_PERI(RTC_C->TCMP, RTC_C_TCMP_TCRDY_OFS))
;
RTC_C->TCMP = offsetValue + offsetDirection;
if (BITBAND_PERI(RTC_C->TCMP, RTC_C_TCMP_TCOK_OFS))
return true;
else
return false;
}
void COMP_E_setReferenceAccuracy(uint32_t comparator,
uint_fast16_t referenceAccuracy)
{
ASSERT(
(referenceAccuracy == COMP_E_ACCURACY_STATIC)
|| (referenceAccuracy == COMP_E_ACCURACY_CLOCKED));
if (referenceAccuracy)
BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL2.r, CEREFACC_OFS) = 1;
else
BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL2.r, CEREFACC_OFS) = 0;
}
void I2C_masterSendMultiByteNext(uint32_t moduleInstance, uint8_t txData)
{
//If interrupts are not used, poll for flags
if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS))
{
//Poll for transmit interrupt flag.
while
(!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
;
}
//Send single byte data.
EUSCI_B_CMSIS(moduleInstance)->rTXBUF.r = txData;
}
void I2C_masterSendMultiByteStop(uint32_t moduleInstance)
{
//If interrupts are not used, poll for flags
if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS))
{
//Poll for transmit interrupt flag.
while
(!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
;
}
//Send stop condition.
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTXSTP_OFS) = 1;
}
void CS_setReferenceOscillatorFrequency(uint8_t referenceFrequency)
{
ASSERT(
referenceFrequency == CS_REFO_32KHZ
|| referenceFrequency == CS_REFO_128KHZ);
/* Unlocking the module */
CS->KEY = CS_KEY;
BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS) = referenceFrequency;
/* Locking the module */
BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
}
void PSS_enableHighSidePinToggle(bool activeLow)
{
__PSSUnlock();
if (activeLow)
PSS->rCTL0.r |= (SVMHOE | SVMHOUTPOLAL);
else
{
BITBAND_PERI(PSS->rCTL0.r, SVMHOUTPOLAL_OFS) = 0;
BITBAND_PERI(PSS->rCTL0.r, SVMHOE_OFS) = 1;
}
__PSSLock();
}
uint8_t I2C_masterReceiveSingleByte(uint32_t moduleInstance)
{
//Set USCI in Receive mode
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTR_OFS) = 0;
//Send start
EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r |= (UCTXSTT + UCTXSTP);
//Poll for receive interrupt flag.
while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCRXIFG_OFS))
;
//Send single byte data.
return EUSCI_B_CMSIS(moduleInstance)->rRXBUF.b.bRXBUF;
}
uint_fast8_t PSS_getLowSidePerformanceMode(void)
{
if (BITBAND_PERI(PSS->rCTL0.r, SVSLLP_OFS))
return PSS_NORMAL_PERFORMANCE_MODE;
else
return PSS_FULL_PERFORMANCE_MODE;
}
//*****************************************************************************
//
//! \brief Initializes the SPI Slave block.
//!
//! Upon successful initialization of the SPI slave block, this function will
//! have initailized the slave block, but the SPI Slave block still remains
//! disabled and must be enabled with EUSCI_B_SPI_enable()
//!
//! \param baseAddress is the base address of the EUSCI_B_SPI Slave module.
//! \param msbFirst controls the direction of the receive and transmit shift
//! register.
//! Valid values are:
//! - \b EUSCI_B_SPI_MSB_FIRST
//! - \b EUSCI_B_SPI_LSB_FIRST [Default]
//! \param clockPhase is clock phase select.
//! Valid values are:
//! - \b EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
//! [Default]
//! - \b EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
//! \param clockPolarity is clock polarity select
//! Valid values are:
//! - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
//! - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default]
//! \param spiMode is SPI mode select
//! Valid values are:
//! - \b EUSCI_B_SPI_3PIN
//! - \b EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH
//! - \b EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW
//!
//! Modified bits are \b UCMSB, \b UCMST, \b UC7BIT, \b UCCKPL, \b UCCKPH, \b
//! UCMODE and \b UCSWRST of \b UCAxCTLW0 register.
//!
//! \return STATUS_SUCCESS
//
//*****************************************************************************
bool EUSCI_B_SPI_slaveInit(uint32_t baseAddress, uint16_t msbFirst,
uint16_t clockPhase, uint16_t clockPolarity, uint16_t spiMode)
{
ASSERT(
(EUSCI_B_SPI_MSB_FIRST == msbFirst)
|| (EUSCI_B_SPI_LSB_FIRST == msbFirst));
ASSERT(
(EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
== clockPhase)
|| (EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
== clockPhase));
ASSERT(
(EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == clockPolarity)
|| (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW
== clockPolarity));
ASSERT(
(EUSCI_B_SPI_3PIN == spiMode)
|| (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH == spiMode)
|| (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW == spiMode));
//Disable USCI Module
BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
//Reset OFS_UCBxCTLW0 register
EUSCI_B_CMSIS(baseAddress)->rCTLW0.r = (EUSCI_B_CMSIS(baseAddress)->rCTLW0.r
& ~(UCMSB + UC7BIT + UCMST + UCCKPL + UCCKPH + UCMODE_3))
| (clockPhase + clockPolarity + msbFirst + UCSYNC + spiMode);
return true;
}
void COMP_E_setReferenceVoltage(uint32_t comparator,
uint_fast16_t supplyVoltageReferenceBase,
uint_fast16_t lowerLimitSupplyVoltageFractionOf32,
uint_fast16_t upperLimitSupplyVoltageFractionOf32)
{
ASSERT(supplyVoltageReferenceBase <= COMP_E_VREFBASE2_5V);
ASSERT(upperLimitSupplyVoltageFractionOf32 <= 32);
ASSERT(lowerLimitSupplyVoltageFractionOf32 <= 32); ASSERT(
upperLimitSupplyVoltageFractionOf32
>= lowerLimitSupplyVoltageFractionOf32);
BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL1.r, CEMRVS_OFS) = 0;
COMP_E_CMSIS(comparator)->rCTL2.r &= CERSEL;
// Set Voltage Source(Vcc | Vref, resistor ladder or not)
if (COMP_E_REFERENCE_AMPLIFIER_DISABLED == supplyVoltageReferenceBase)
{
COMP_E_CMSIS(comparator)->rCTL2.r |= CERS_1;
} else if (lowerLimitSupplyVoltageFractionOf32 == 32)
{
COMP_E_CMSIS(comparator)->rCTL2.r |= CERS_3;
} else
{
COMP_E_CMSIS(comparator)->rCTL2.r |= CERS_2;
}
// Set COMPE Control 2 Register
COMP_E_CMSIS(comparator)->rCTL2.r |= supplyVoltageReferenceBase
+ ((upperLimitSupplyVoltageFractionOf32 - 1) << 8)
+ (lowerLimitSupplyVoltageFractionOf32 - 1);
}
void CS_tuneDCOFrequency(int16_t tuneParameter)
{
CS->KEY = CS_KEY;
uint16_t dcoTuneMask = 0x1FFF;
uint16_t dcoTuneSigned = 0x1000;
if (TLV->HWREV > DEVICE_PG1_1) {
dcoTuneMask = 0x3FF;
dcoTuneSigned = 0x200;
}
if (tuneParameter < 0)
{
CS->CTL0 = ((CS->CTL0 & ~dcoTuneMask) | (tuneParameter
& dcoTuneMask) | dcoTuneSigned);
}
else
{
CS->CTL0 = ((CS->CTL0 & ~dcoTuneMask) | (tuneParameter
& dcoTuneMask));
}
BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
}
bool PCM_gotoLPM3(void)
{
uint_fast8_t bCurrentPowerState;
uint_fast8_t currentPowerMode;
/* If we are in the middle of a state transition, return false */
if (BITBAND_PERI(PCM->CTL1, PCM_CTL1_PMR_BUSY_OFS))
return false;
/* If we are in the middle of a shutdown, return false */
if ((PCM->CTL0 & PCM_CTL0_LPMR_MASK) == PCM_CTL0_LPMR_10
|| (PCM->CTL0 & PCM_CTL0_LPMR_MASK) == PCM_CTL0_LPMR_12)
return false;
currentPowerMode = PCM_getPowerMode();
bCurrentPowerState = PCM_getPowerState();
if (currentPowerMode == PCM_DCDC_MODE || currentPowerMode == PCM_LF_MODE)
PCM_setPowerMode(PCM_LDO_MODE);
/* Clearing the SDR */
PCM->CTL0 = (PCM->CTL0 & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_LPMR_MASK)) | PCM_KEY;
/* Setting the sleep deep bit */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
CPU_wfi();
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
return PCM_setPowerState(bCurrentPowerState);
}
uint32_t CS_getBCLK(void)
{
if (BITBAND_PERI(CS->CTL1, CS_CTL1_SELB_OFS))
return _CSComputeCLKFrequency(CS_REFOCLK_SELECT, CS_CLOCK_DIVIDER_1);
else
return _CSComputeCLKFrequency(CS_LFXTCLK_SELECT, CS_CLOCK_DIVIDER_1);
}
void CS_setDCOExternalResistorCalibration(uint_fast8_t calData,
uint_fast8_t freqRange)
{
uint_fast8_t rselVal;
/* Unlocking the module */
CS->KEY = CS_KEY;
rselVal = (CS->CTL0 | CS_CTL0_DCORSEL_MASK)>>CS_CTL0_DCORSEL_OFS;
CS->CTL0 &= ~CS_CTL0_DCORSEL_MASK;
if( (freqRange == CS_OVER32MHZ) && ( TLV->HWREV > DEVICE_PG1_1))
{
CS->DCOERCAL1 &= ~CS_DCOERCAL1_DCO_FCAL_RSEL5_MASK;
CS->DCOERCAL1 |= (calData);
}
else
{
CS->DCOERCAL0 &= ~CS_DCOERCAL0_DCO_FCAL_RSEL04_MASK;
CS->DCOERCAL0 |= (calData)<<CS_DCOERCAL0_DCO_FCAL_RSEL04_OFS;
}
CS->CTL0 |= (rselVal)<<CS_CTL0_DCORSEL_OFS;
/* Locking the module */
BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
}
