/*****************************************************************************
* Function Name : tca_i2c_setgpio(int ch)
* Description: I2C port configuration
* input parameter:
* int core; // I2C Core
* int ch; // I2C master channel
******************************************************************************/
void tca_i2c_setgpio(int core, int ch)
{
PGPIO gpio = (PGPIO)tcc_p2v(HwGPIO_BASE);
switch (core) {
case 0:
{
if (ch == 0) {
BITCSET(gpio->GPAFN0, (Hw8-Hw0), Hw4|Hw0); /* GPIO_A[1:0] */
BITSET(gpio->GPAEN, Hw1|Hw0);
BITCLR(gpio->GPADAT, Hw1|Hw0);
} else if (ch == 1) {
BITCSET(gpio->GPAFN0, (Hw32-Hw28), Hw28); /* GPIO_A[7] */
BITCSET(gpio->GPAFN1, (Hw4-Hw0), Hw0); /* GPIO_A[8] */
BITSET(gpio->GPAEN, Hw8|Hw7);
BITCLR(gpio->GPADAT, Hw8|Hw7);
}
break;
}
case 1:
{
if (ch == 0) {
/* Not used */
} else if (ch == 1) {
/* Not used */
}
break;
}
}
}
/**
* \brief Disable SPI and change to GPIO
*/
void epd_spi_detach(void) {
BITCLR(SPISEL, SPICLK_PIN + SPIMOSI_PIN + SPIMISO_PIN);
BITCLR(SPISEL2, SPICLK_PIN + SPIMOSI_PIN + SPIMISO_PIN);
//config_gpio_dir_o(SPICLK_PORT,SPICLK_PIN);
//config_gpio_dir_o(SPIMOSI_PORT,SPIMOSI_PIN);
//config_gpio_dir_o(SPIMISO_PORT,SPIMISO_PIN);
SPIMISO_low();
SPIMOSI_low();
SPICLK_low();
spi_flag = FALSE;
}
void tchal_reset_device(void)
{
#ifdef __USE_TC_CPU__
tcbd_debug(DEBUG_TCHAL, "\n");
#if defined(__CSPI_ONLY__)
/* select peripheral mode as SPI */
#if defined(__USE_DXB1_IRQ__)
BITCLR(RGPIO->GPAFN1, Hw16 - Hw12); /* DXB1_IRQ Set GPIO mode*/
BITSET(RGPIO->GPAEN, Hw11); /* DXB1_IRQ output mode*/
BITCLR(RGPIO->GPADAT, Hw11); /* DXB1_IRQ clear*/
#elif defined(__USE_DXB0_IRQ__)
BITCLR(RGPIO->GPDFN1, Hw8 - Hw4); /* DXB0_IRQ Set GPIO mode*/
BITSET(RGPIO->GPDEN, Hw9); /* DXB0_IRQ output mode*/
BITCLR(RGPIO->GPDDAT, Hw9); /* DXB0_IRQ clear*/
#endif /*__USE_DXB1_IRQ__*/
#endif /*__CSPI_ONLY__*/
/* reset */
#if defined(__CSPI_ONLY__)
BITCLR(RGPIO->GPEFN1, Hw16 - Hw12); /* DXB1_RST# Set GPIO mode */
BITSET(RGPIO->GPEEN, Hw11); /* DXB1_RST# Set GPIO Output mode*/
BITCLR(RGPIO->GPEDAT, Hw11); /* DXB1_RST# Clear */
tcpal_msleep(10);
BITSET(RGPIO->GPEDAT, Hw11); /* DXB1_RST# Set*/
#elif defined(__I2C_STS__)
BITCLR(RGPIO->GPDFN1, Hw4 - Hw0); /* DXB0_RST# Set GPIO mode */
BITSET(RGPIO->GPDEN, Hw8); /* DXB0_RST# Set GPIO Output mode*/
BITCLR(RGPIO->GPDDAT, Hw8); /* DXB0_RST# Clear */
tcpal_msleep(10);
BITSET(RGPIO->GPDDAT, Hw8); /* DXB0_RST# Set*/
#else /*__CSPI_ONLY__ || __I2C_STS__*/
#error "you must define __CSPI_ONLY__ or __I2C_STS__"
#endif /*!__CSPI_ONLY__ && !__I2C_STS__*/
#endif
}
void tchal_power_down_device(void)
{
#ifdef __USE_TC_CPU__
tcbd_debug(DEBUG_TCHAL, "\n");
BITCLR(RGPIO->GPEFN0, Hw16 - Hw12);
BITSET(RGPIO->GPEEN, Hw3);/* DXB1_PD Set GPIO Output mode*/
BITCLR(RGPIO->GPEDAT, Hw3);/* DXB1_PD Clear*/
#if defined(__CSPI_ONLY__)
BITCLR(RGPIO->GPEDAT, Hw11);/* DXB1_RST# Clear*/
#elif defined(__I2C_STS__)
BITCLR(RGPIO->GPDDAT, Hw8);/* DXB0_RST# Clear */
#else
#error "you must define __CSPI_ONLY__ or __I2C_STS__"
#endif
#endif
}
void tchal_power_on_device(void)
{
#ifdef __USE_TC_CPU__
tcbd_debug(DEBUG_TCHAL, "\n");
BITCLR(RGPIO->GPEFN0, Hw16 - Hw12);/* DXB1_PD Set GPIO mode*/
BITSET(RGPIO->GPEEN, Hw3);/* DXB1_PD Set GPIO Output mode*/
BITCLR(RGPIO->GPEDAT, Hw3);/* DXB1_PD Clear*/
tcpal_msleep(10);
BITSET(RGPIO->GPEDAT, Hw3);/* DXB1_PD Set*/
tcpal_msleep(10);
tchal_reset_device();
tchal_irq_setup();
#endif
}
/** Change stepper ic controller direction. 1 is CW, 0 is CCW seen from top
*/
void stepper_set_direction( int8_t dir )
{
if(dir >= 1)
BITSET(PORTL,PL3); //Rotation direcion CW
else
BITCLR(PORTL,PL3); //Rotation direcion to CCW
}
static void
tcc88xx_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *c)
{
unsigned long flags;
#if defined(TICKLESS_DEBUG_TCC)
printk("%s: mode %s... %d\n", __func__,
mode == CLOCK_EVT_MODE_ONESHOT ? "ONESHOT" :
mode == CLOCK_EVT_MODE_UNUSED ? "UNUSED" :
mode == CLOCK_EVT_MODE_SHUTDOWN ? "SHUTDOWN" :
mode == CLOCK_EVT_MODE_RESUME ? "RESUME" :
mode == CLOCK_EVT_MODE_PERIODIC ? "PERIODIC" : "non",
gTimer_cnt++);
#endif
switch (mode) {
case CLOCK_EVT_MODE_ONESHOT:
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
raw_local_irq_save(flags);
BITCLR(pTIMER->TC32IRQ, Hw16); /* Disable interrupt when the counter value matched with CMP0 */
BITSET(pPIC->CLR0, TCC_ENABLE_BIT(INT_TC32)); /* PIC Interrupt clear */
if(pTIMER->TC32IRQ & Hw31) /* IRQ clear */
BITSET(pTIMER->TC32IRQ, Hw31);
raw_local_irq_restore(flags);
break;
case CLOCK_EVT_MODE_RESUME:
case CLOCK_EVT_MODE_PERIODIC:
break;
}
}
void CIF_OpStop(char wait_SOF, char sw_reset )
{
#if defined(CONFIG_ARCH_TCC79X)
if(wait_SOF)
{
BITSET(HwCIF->CIRQ, HwCIRQ_SOF);
CIF_WaitFrameSync(400);
BITSET(HwCIF->CIRQ, HwCIRQ_SOF);
}
#elif defined(CONFIG_ARCH_TCC92XX) || defined(CONFIG_ARCH_TCC93XX) || defined(CONFIG_ARCH_TCC88XX)
volatile PCIF pCIF = (PCIF)tcc_p2v(HwCIF_BASE);
#if defined(CONFIG_ARCH_TCC92XX)
volatile PDDICONFIG pDDICfg = (PDDICONFIG)tcc_p2v(HwDDI_CONFIG_BASE);
#elif defined(CONFIG_ARCH_TCC93XX) || defined(CONFIG_ARCH_TCC88XX)
volatile PCAMBUSCFG pCamBusCfg = (PCAMBUSCFG)tcc_p2v(HwCAMBUSCFG_BASE);
#endif
if(wait_SOF)
{
BITSET(pCIF->CIRQ, HwCIRQ_SOF);
CIF_WaitFrameSync(400);
BITSET(pCIF->CIRQ, HwCIRQ_SOF);
}
#elif defined(CONFIG_ARCH_TCC892X)
// In case of 892X, we have to add.
#endif
CIF_ONOFF(OFF);
if(sw_reset)
{
#if defined(CONFIG_ARCH_TCC79X)
BITSET(HwSWRESET, HwSWRESET_CIC_ON);
BITCLR(HwSWRESET, HwSWRESET_CIC_ON);
#elif defined(CONFIG_ARCH_TCC92XX)
BITSET(pDDICfg->SWRESET, HwDDIC_SWRESET_CIF); // Reset
BITCLR(pDDICfg->SWRESET, HwDDIC_SWRESET_CIF); // Normal
#elif defined(CONFIG_ARCH_TCC93XX) || defined(CONFIG_ARCH_TCC88XX)
BITSET(pCamBusCfg->SoftResetRegister, HwCAMBUS_SWRESET_CIF); // Reset
BITCLR(pCamBusCfg->SoftResetRegister, HwCAMBUS_SWRESET_CIF); // Normal
#elif defined(CONFIG_ARCH_TCC892X)
// In case of 892X, we have to add.
#endif
}
}
void tchal_irq_setup(void)
{
#ifdef __USE_TC_CPU__
#if defined(__USE_DXB1_IRQ__)
BITCLR(RGPIO->GPAFN1, Hw16 - Hw12); /* DXB1_IRQ Set GPIO mode*/
BITCLR(RGPIO->GPAEN, Hw11); /* DXB1_IRQ input mode*/
BITCSET(RGPIO->EINTSEL0, Hw32 - Hw24, 11<<24); /*GPIO_A11*/
#elif defined(__USE_DXB0_IRQ__)
BITCLR(RGPIO->GPDFN1, Hw8 - Hw4); /* DXB0_IRQ Set GPIO mode*/
BITCLR(RGPIO->GPDEN, Hw9); /* DXB0_IRQ input mode*/
BITCSET(RGPIO->EINTSEL0, Hw32 - Hw24, 20<<24); /*GPIO_D9*/
#endif /*__USE_DXB1_IRQ__*/
BITSET(RPIC->POL0, 1<<IRQ_TC317X);
#endif
}
void
EvrInput::levelHighSet(bool v)
{
if(v)
BITCLR(NAT,32, base, InputMapFP(idx), InputMapFP_lvl);
else
BITSET(NAT,32, base, InputMapFP(idx), InputMapFP_lvl);
}
void
EvrInput::edgeRiseSet(bool v)
{
if(v)
BITCLR(NAT,32, base, InputMapFP(idx), InputMapFP_edge);
else
BITSET(NAT,32, base, InputMapFP(idx), InputMapFP_edge);
}
void internal_tve_enable(unsigned int type, unsigned int onoff)
{
volatile PNTSCPAL pHwTVE = (volatile PNTSCPAL)tcc_p2v(HwTVE_BASE);
volatile PNTSCPAL_ENCODER_CTRL pHwTVE_VEN = (volatile PNTSCPAL_ENCODER_CTRL)tcc_p2v(HwNTSCPAL_ENC_CTRL_BASE);
if(onoff)
{
internal_tve_set_config(type);
BITSET(pHwTVE_VEN->VENCON.nREG, HwTVEVENCON_EN_EN);
BITSET(pHwTVE->DACPD.nREG, HwTVEDACPD_PD_EN);
BITCLR(pHwTVE->ECMDA.nREG, HwTVECMDA_PWDENC_PD);
}
else
{
BITCLR(pHwTVE_VEN->VENCON.nREG, HwTVEVENCON_EN_EN);
BITCLR(pHwTVE->DACPD.nREG, HwTVEDACPD_PD_EN);
BITSET(pHwTVE->ECMDA.nREG, HwTVECMDA_PWDENC_PD);
}
}
/*****************************************************************************
* Function Name : static void remocon_irq_init(void);
* Description : IRQ register init
* Arguments :
******************************************************************************/
static void remocon_irq_init(void)
{
volatile PPIC pPIC = (volatile PPIC)tcc_p2v(HwPIC_BASE);
#if defined(CONFIG_ARCH_TCC892X)
BITSET(pPIC->IEN1.nREG, Hw10);
BITSET(pPIC->SEL1.nREG, Hw10);
BITSET(pPIC->INTMSK1.nREG, Hw10);
BITCLR(pPIC->POL1.nREG, Hw10);
BITSET(pPIC->MODE1.nREG, Hw10);
BITCLR(pPIC->MODEA1.nREG, Hw10);
#else
BITSET(pPIC->IEN1, HwINT1_RMT);
BITSET(pPIC->SEL1, HwINT1_RMT);
BITSET(pPIC->INTMSK1, HwINT1_RMT);
BITCLR(pPIC->POL1, HwINT1_RMT);
BITSET(pPIC->MODE1, HwINT1_RMT);
BITCLR(pPIC->MODEA1, HwINT1_RMT);
#endif
}
/*
* BroadCasting DXB Interface.
*/
void init_bc_interrupt(tcc_intr_data_t *tcc_intr)
{
PGPIO pGPIO = (volatile PGPIO)tcc_p2v(HwGPIO_BASE);
tcc_intr->irq = INT_TSD;
tcc_intr->irq_bit = (1 << INT_TSD);
tcc_intr->irq_regs = (volatile PPIC)tcc_p2v(HwPIC_BASE);
/* DXB0_IRQ - GPIO_E5 - ExINT3 */
BITCLR(pGPIO->GPEFN0, Hw24-Hw20); // gpio
BITCLR(pGPIO->GPEEN, Hw5); // input mode
BITCSET(pGPIO->EINTSEL0, Hw30-Hw24, (53<<24));
BITSET(tcc_intr->irq_regs->EI37SEL, Hw3);
/* Int trigger setting */
BITCLR(tcc_intr->irq_regs->MODE0, tcc_intr->irq_bit); // edge-triggered
BITCLR(tcc_intr->irq_regs->MODEA0, tcc_intr->irq_bit); // single-edge
BITCLR(tcc_intr->irq_regs->POL0, tcc_intr->irq_bit); // active-high
}
/** Generate step
*/
void stepper_advance()
{
BITCLR(PORTL,PL0);
_delay_us(900); // Hold line down to advance one step
BITSET(PORTL,PL0);
// check direction to update step counter
if( stepper_get_direction() )
curr_step_num++ ;
else
curr_step_num-- ;
}
/**
* Clear a item of event which you don't care anymore.
* @ref sockwatch_run stop to detect the item on the socket.
* It is possible to set plural item of event at the same time.
*
* @ingroup sockwatch_module
* @param sock The socket number to clear
* @param item The item of event to clear
* @return RET_OK: Success
* @return RET_NOK: Error
*/
int8_t sockwatch_clr(uint8_t sock, uint8_t item)
{
DBGA("WATCH Clear - sock(%d), item(0x%x)", sock, item);
if(sock >= TOTAL_SOCK_NUM) {
ERRA("wrong sock(%d)", sock);
return RET_NOK;
}
BITCLR(watch_sock[sock], 0x7F & item);
return RET_OK;
}
void
EvrInput::extModeSet(TrigMode m)
{
switch(m){
case TrigNone:
// Disable both level and edge
BITCLR(NAT,32, base, InputMapFP(idx), InputMapFP_eedg);
BITCLR(NAT,32, base, InputMapFP(idx), InputMapFP_elvl);
break;
case TrigLevel:
// disable edge, enable level
BITCLR(NAT,32, base, InputMapFP(idx), InputMapFP_eedg);
BITSET(NAT,32, base, InputMapFP(idx), InputMapFP_elvl);
break;
case TrigEdge:
// disable level, enable edge
BITSET(NAT,32, base, InputMapFP(idx), InputMapFP_eedg);
BITCLR(NAT,32, base, InputMapFP(idx), InputMapFP_elvl);
break;
}
}
void Gre2d_Set_interrupt(char onoff)
{
PPIC pHwPIC;
pHwPIC = (volatile PPIC)tcc_p2v(HwPIC_BASE);
#if defined(CONFIG_ARCH_TCC92XX) || defined(CONFIG_ARCH_TCC93XX)
if(onoff)
{
BITSET(pHwPIC->CLR0, HwINT0_G2D);
BITCLR(pHwPIC->POL0, HwINT0_G2D);
BITSET(pHwPIC->SEL0, HwINT0_G2D);
BITSET(pHwPIC->IEN0, HwINT0_G2D);
BITSET(pHwPIC->MODE0, HwINT0_G2D);
}
else
{
BITCLR(pHwPIC->IEN0, HwINT0_G2D);
}
#elif defined(CONFIG_ARCH_TCC892X)
if(onoff) {
}
else {
}
#else
if(onoff)
{
BITSET(pHwPIC->CLR1, HwINT1_G2D);
BITCLR(pHwPIC->POL1, HwINT1_G2D);
BITSET(pHwPIC->SEL1, HwINT1_G2D);
BITSET(pHwPIC->IEN1, HwINT1_G2D);
BITSET(pHwPIC->MODE1, HwINT1_G2D);
}
else
{
BITCLR(pHwPIC->IEN1, HwINT1_G2D);
}
#endif//
}
static struct lcd_panel * lcdc_io_init(unsigned char lcdc_num)
{
struct lcd_panel *panel;
unsigned int lclk;
#if 0
// reset VIOD
BITSET(pDDICfg->SWRESET, Hw3);
BITSET(pDDICfg->SWRESET, Hw2);
BITCLR(pDDICfg->SWRESET, Hw3);
BITCLR(pDDICfg->SWRESET, Hw2);
#endif//
panel = tccfb_get_panel();
panel->dev.power_on = GPIO_LCD_ON;
panel->dev.display_on = GPIO_LCD_DISPLAY;
panel->dev.bl_on = GPIO_LCD_BL;
panel->dev.reset = GPIO_LCD_RESET;
panel->dev.lcdc_num = lcdc_num;
panel->init(panel);
if(lcdc_num)
{
tca_ckc_setperi(PERI_LCD1,ENABLE, panel->clk_freq * panel->clk_div);
lclk = tca_ckc_getperi(PERI_LCD1);
}
else
{
tca_ckc_setperi(PERI_LCD0,ENABLE, panel->clk_freq * panel->clk_div);
lclk = tca_ckc_getperi(PERI_LCD0);
}
printf("telechips tcc88xx %s lcdc:%d clk:%d set clk:%d \n", __func__, lcdc_num, panel->clk_freq, lclk);
panel->set_power(panel, 1);
printf("%s end\n", __func__);
return panel;
}
static int eth16i_probe_port(int ioaddr)
{
int i;
int retcode;
unsigned char dummy_packet[64];
/* Powerup the chip */
outb(0xc0 | POWERUP, ioaddr + CONFIG_REG_1);
BITSET(ioaddr + CONFIG_REG_0, DLC_EN);
eth16i_select_regbank(NODE_ID_RB, ioaddr);
for(i = 0; i < 6; i++) {
dummy_packet[i] = inb(ioaddr + NODE_ID_0 + i);
dummy_packet[i+6] = inb(ioaddr + NODE_ID_0 + i);
}
dummy_packet[12] = 0x00;
dummy_packet[13] = 0x04;
memset(dummy_packet + 14, 0, sizeof(dummy_packet) - 14);
eth16i_select_regbank(2, ioaddr);
for(i = 0; i < 3; i++) {
BITSET(ioaddr + CONFIG_REG_0, DLC_EN);
BITCLR(ioaddr + CONFIG_REG_0, DLC_EN);
eth16i_set_port(ioaddr, i);
if(eth16i_debug > 1)
printk(KERN_DEBUG "Set port number %d\n", i);
retcode = eth16i_send_probe_packet(ioaddr, dummy_packet, 64);
if(retcode == 0) {
retcode = eth16i_receive_probe_packet(ioaddr);
if(retcode != -1) {
if(eth16i_debug > 1)
printk(KERN_DEBUG "Eth16i interface port found at %d\n", i);
return i;
}
}
else {
if(eth16i_debug > 1)
printk(KERN_DEBUG "TRANSMIT_DONE timeout when probing interface port\n");
}
}
if( eth16i_debug > 1)
printk(KERN_DEBUG "Using default port\n");
return E_PORT_BNC;
}
void Gre2d_SW_reset(void)
{
//SW Reset
#ifdef CONFIG_ARCH_TCC92XX
BITSET(HwGRPBUS->GRPBUS_SWRESET, HwGRP_OM);
Gre2d_DELAY(100);
BITCLR(HwGRPBUS->GRPBUS_SWRESET, HwGRP_OM);
#else
//tcc88xx // tcc93xx
#endif//
Gre2d_DELAY(200);
}
BOOL ACCEL_readID(threeAxis_t* result) {
while(!SPI_acquirePort());
BITCLR(POUT_ACCEL_CS, PIN_ACCEL_CS);
SPI_transaction(gpRxBuf, (uint8_t*)ADXL_READ_DEVID, sizeof(ADXL_READ_DEVID));
BITSET(POUT_ACCEL_CS, PIN_ACCEL_CS);
SPI_releasePort();
result->x = gpRxBuf[2];
return SUCCESS;
}
static int tcc_tsif_dmastop(struct tcc_tsif_handle *h)
{
volatile PGDMACTRL dma_regs;
if(h->dma_controller == 0)
dma_regs = (volatile PGDMACTRL)tcc_p2v(HwGDMA0_BASE);
else if(h->dma_controller == 1)
dma_regs = (volatile PGDMACTRL)tcc_p2v(HwGDMA1_BASE);
else if(h->dma_controller == 2)
dma_regs = (volatile PGDMACTRL)tcc_p2v(HwGDMA2_BASE);
if(h->dma_ch == 0) BITCLR(dma_regs->CHCTRL0.nREG, Hw0); //dma disable
else if(h->dma_ch == 1) BITCLR(dma_regs->CHCTRL1.nREG, Hw0); //dma disable
else BITCLR(dma_regs->CHCTRL2.nREG, Hw0); //dma disable
BITCLR(h->regs->TSRXCR, Hw31); //tsif disable
#ifdef DEBUG_INFO
printk("%s\n", __func__);
#endif
return 0;
}
void SDMMC_ms_delay(unsigned long ul_ms)
{
#define TCFG_TCKSEL(x) (x<<4)
#define TCFG_CON Hw1
#define TCFG_EN Hw0
PTIMER pTIMER = (TIMER*)TCC_TIMER_BASE;
volatile unsigned int baseCounter;
volatile unsigned int timed;
#if defined(TCC892X_EMMC_BOOT)
pTIMER->TCFG1.nREG= TCFG_TCKSEL(5)|TCFG_CON|TCFG_EN;
baseCounter = pTIMER->TCNT1.bREG.TCNT;
do{
timed = (pTIMER->TCNT1.bREG.TCNT - baseCounter) & 0xFFFF;
}while(timed < 12 * ul_ms);//1ms
BITCLR(pTIMER->TCFG1.nREG, TCFG_EN);
#else
pTIMER->TCFG1= TCFG_TCKSEL(5)|TCFG_CON|TCFG_EN;
baseCounter = pTIMER->TCNT1;
do{
timed = (pTIMER->TCNT1 - baseCounter) & 0xFFFF;
}while(timed < 12 * ul_ms);//1ms
BITCLR(pTIMER->TCFG1, TCFG_EN);
#endif
}
BOOL ACCEL_initialize() {
// TODO Figure out optimal ADXL configuration for single measurement
while(!SPI_acquirePort());
//BITSET(POUT_ACCEL_EN, PIN_ACCEL_EN);
//BITSET(POUT_ACCEL_CS, PIN_ACCEL_CS);
//TODO find the proper length of delay
BITCLR(POUT_ACCEL_CS, PIN_ACCEL_CS);
BITCLR(POUT_ACCEL_EN, PIN_ACCEL_EN);
SPI_transaction(gpRxBuf, (uint8_t*)ADXL_CONFIG_MEAS, sizeof(ADXL_CONFIG_MEAS));
BITSET(POUT_ACCEL_CS, PIN_ACCEL_EN);
BITSET(POUT_ACCEL_CS, PIN_ACCEL_CS);
SPI_releasePort();
//__delay_cycles(5000);
//Timer_LooseDelay(LP_LSDLY_200MS);// To let ADXL start measuring? How much time is actually required here, if any?
// TODO Use a pin interrupt to let us know when first measurement is ready
return SUCCESS;
}
static irqreturn_t tcc88xx_ost0_interrupt(int irq, void *dev_id)
{
struct clock_event_device *c = dev_id;
BITCLR(pTIMER->TC32IRQ, Hw16); /* Disable interrupt when the counter value matched with CMP0 */
BITSET(pPIC->CLR0, TCC_ENABLE_BIT(irq)); /* Interrupt clear */
if(pTIMER->TC32IRQ & Hw31) /* IRQ clear */
BITSET(pTIMER->TC32IRQ, Hw31);
c->event_handler(c);
#if defined(TICKLESS_DEBUG_TCC)
gInt_cnt++;
#endif
return IRQ_HANDLED;
}
/**
* Grab one sample from the ADXL362 accelerometer
*/
BOOL ACCEL_singleSample(threeAxis_t* result) {
while(!SPI_acquirePort());
BITCLR(POUT_ACCEL_CS, PIN_ACCEL_CS);
SPI_transaction(gpRxBuf, (uint8_t*)ADXL_READ_XYZ_8BIT, sizeof(ADXL_READ_XYZ_8BIT));
BITSET(POUT_ACCEL_CS, PIN_ACCEL_CS);
SPI_releasePort();
result->x = gpRxBuf[2];
result->y = gpRxBuf[3];
result->z = gpRxBuf[4];
return SUCCESS;
}
long io_interrupt(tcc_intr_data_t *tcc_intr, long flag)
{
/* NOTE: irq_regs->XXX0, XXX1 */
long ret = 0;
if (flag == 0) {
BITSET(tcc_intr->irq_regs->CLR0, tcc_intr->irq_bit); // clear intr
BITCLR(tcc_intr->irq_regs->INTMSK0, tcc_intr->irq_bit); // disable intr
} else if (flag == 1) {
BITSET(tcc_intr->irq_regs->CLR0, tcc_intr->irq_bit);
BITSET(tcc_intr->irq_regs->INTMSK0, tcc_intr->irq_bit); // enable intr
} else if (flag == 2) {
ret = (tcc_intr->irq_regs->INTMSK0 & tcc_intr->irq_bit)?1:0; // get int-mask status
} else {
ret = -1;
}
return ret;
}
static void tca_clear_pid_tables(struct tcc_tsif_handle *h)
{
int i;
#if defined(SUPPORT_PIDFILTER_DMA)
volatile unsigned long* PIDT;
for (i = 0; i < 32; i++) {
PIDT = (volatile unsigned long *)tcc_p2v(HwTSIF_PIDT(i));
*PIDT = 0;
}
#endif
#ifdef SUPPORT_PIDFILTER_INTERNAL
for (i = 0; i < 16; i++) {
BITCLR(h->regs->TSPID[i], (Hw32-Hw0));
}
// printk("%s\n", __func__);
#endif
}
/**
* \brief Configure SPI
*/
void epd_spi_init(void) {
if (spi_flag)
return;
spi_flag = TRUE;
//config i/o
config_gpio_dir_o(SPICLK_PORT, SPICLK_PIN);
config_gpio_dir_o(SPIMOSI_PORT, SPIMOSI_PIN);
config_gpio_dir_i(SPIMISO_PORT, SPIMISO_PIN);
BITSET(SPISEL, SPICLK_PIN + SPIMOSI_PIN + SPIMISO_PIN);
BITSET(SPISEL2, SPICLK_PIN + SPIMOSI_PIN + SPIMISO_PIN);
//comfig SPI
SPICTL0 = UCCKPH | UCMST | UCSYNC | UCMSB;
SPICTL1 = UCSSEL_2 + UCSWRST;
SPIBR0 = 2; //16MHz/2=8MHz
SPIBR1 = 0;
BITSET(REN (SPIMISO_PORT), SPIMISO_PIN);
BITCLR(SPICTL1, UCSWRST);
}
