static int mc13892_sw_dvs_set_voltage(struct regulator *reg, int uV) { unsigned int register_val = 0, register_mask = 0; unsigned int register1 = 0; int voltage, sw = reg->id, mV = uV / 1000, hi; hi = mc13892_get_sw_hi_bit(sw); voltage = mc13892_get_voltage_value(hi, mV); switch (sw) { case MC13892_SW1: register1 = REG_SW_0; register_val = BITFVAL(SW1_DVS, voltage); register_mask = BITFMASK(SW1_DVS); break; case MC13892_SW2: register1 = REG_SW_1; register_val = BITFVAL(SW2_DVS, voltage); register_mask = BITFMASK(SW2_DVS); break; default: return -EINVAL; } return (pmic_write_reg(register1, register_val, register_mask)); }
static int tps6518x_display_disable(struct regulator_dev *reg) { struct tps6518x *tps6518x = rdev_get_drvdata(reg); unsigned int cur_reg_val; /* current register value to modify */ unsigned int fld_mask; /* register mask for bitfield to modify */ unsigned int fld_val; /* new bitfield value to write */ unsigned int new_reg_val; /* new register value to write */ if (tps6518x->revID == 65182) { epdc_pwr0_disable(reg); } else { /* turn off display regulators */ cur_reg_val = tps65180_current_Enable_Register & 0x3f; fld_mask = BITFMASK(VCOM_EN) | BITFMASK(STANDBY); fld_val = BITFVAL(VCOM_EN, false) | BITFVAL(STANDBY, true); new_reg_val = tps65180_current_Enable_Register = to_reg_val(cur_reg_val, fld_mask, fld_val); tps6518x_reg_write(REG_TPS65180_ENABLE, new_reg_val); } msleep(tps6518x->max_wait); return 0; }
static int max17135_vcom_set_voltage(struct regulator_dev *reg, int minuV, int uV, unsigned *selector) { struct max17135 *max17135 = rdev_get_drvdata(reg); unsigned int reg_val; int vcom_read; if ((uV < vcom_data[max17135->pass_num-1].vcom_min_uV) || (uV > vcom_data[max17135->pass_num-1].vcom_max_uV)) return -EINVAL; max17135_reg_read(REG_MAX17135_DVR, ®_val); /* * Only program VCOM if it is not set to the desired value. * Programming VCOM excessively degrades ability to keep * DVR register value persistent. */ vcom_read = vcom_rs_to_uV(reg_val, max17135->pass_num-1); if (vcom_read != max17135->vcom_uV) { reg_val &= ~BITFMASK(DVR); reg_val |= BITFVAL(DVR, vcom_uV_to_rs(uV, max17135->pass_num-1)); max17135_reg_write(REG_MAX17135_DVR, reg_val); reg_val = BITFVAL(CTRL_DVR, true); /* shift to correct bit */ return max17135_reg_write(REG_MAX17135_PRGM_CTRL, reg_val); } return 0; }
PMIC_STATUS mc13892_bklit_set_blink_p(enum lit_channel channel, int period) { unsigned int mask; unsigned int value; int reg; switch (channel) { case LIT_RED: value = BITFVAL(BIT_BP_RED, period); mask = BITFMASK(BIT_BP_RED); reg = REG_LED_CTL2; break; case LIT_GREEN: value = BITFVAL(BIT_BP_GREEN, period); mask = BITFMASK(BIT_BP_GREEN); reg = REG_LED_CTL2; break; case LIT_BLUE: value = BITFVAL(BIT_BP_BLUE, period); mask = BITFMASK(BIT_BP_BLUE); reg = REG_LED_CTL3; break; default: return PMIC_PARAMETER_ERROR; } CHECK_ERROR(pmic_write_reg(reg, value, mask)); return PMIC_SUCCESS; }
static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) { unsigned int tod_reg_val = 0; unsigned int day_reg_val = 0; unsigned int mask, value; unsigned long time; if (rtc_valid_tm(&alrm->time)) return -1; rtc_tm_to_time(&alrm->time, &time); tod_reg_val = time % 86400; day_reg_val = time / 86400; mask = BITFMASK(RTCALARM_TIME); value = BITFVAL(RTCALARM_TIME, tod_reg_val); CHECK_ERROR(pmic_write_reg(REG_RTC_ALARM, value, mask)); mask = BITFMASK(RTCALARM_DAY); value = BITFVAL(RTCALARM_DAY, day_reg_val); CHECK_ERROR(pmic_write_reg(REG_RTC_DAY_ALARM, value, mask)); return 0; }
PMIC_STATUS mc13892_bklit_set_hi_current(enum lit_channel channel, int mode) { unsigned int mask; unsigned int value; int reg; switch (channel) { case LIT_MAIN: value = BITFVAL(BIT_HC_MAIN, mode); mask = BITFMASK(BIT_HC_MAIN); reg = REG_LED_CTL0; break; case LIT_AUX: value = BITFVAL(BIT_HC_AUX, mode); mask = BITFMASK(BIT_HC_AUX); reg = REG_LED_CTL0; break; case LIT_KEY: value = BITFVAL(BIT_HC_KEY, mode); mask = BITFMASK(BIT_HC_KEY); reg = REG_LED_CTL1; break; default: return PMIC_PARAMETER_ERROR; } CHECK_ERROR(pmic_write_reg(reg, value, mask)); return PMIC_SUCCESS; }
static int mc13892_gpo_disable(struct regulator *reg) { unsigned int register_val = 0, register_mask = 0; unsigned int register1; int gpo = reg->id; switch (gpo) { case MC13892_GPO1: register_val = BITFVAL(GPO1_EN, GPO1_EN_DISABLE); register_mask = BITFMASK(GPO1_EN); break; case MC13892_GPO2: register_val = BITFVAL(GPO2_EN, GPO2_EN_DISABLE); register_mask = BITFMASK(GPO2_EN); break; case MC13892_GPO3: register_val = BITFVAL(GPO3_EN, GPO3_EN_DISABLE); register_mask = BITFMASK(GPO3_EN); break; case MC13892_GPO4: register_val = BITFVAL(GPO4_EN, GPO4_EN_DISABLE); register_mask = BITFMASK(GPO4_EN); break; default: return -EINVAL; }; register1 = REG_POWER_MISC; return (pmic_write_reg(register1, register_val, register_mask)); }
static int mxc_rtc_set_time(struct device *dev, struct rtc_time *tm) { unsigned int tod_reg_val = 0; unsigned int day_reg_val, day_reg_val2 = 0; unsigned int mask, value; unsigned long time; if (rtc_valid_tm(tm)) return -1; rtc_tm_to_time(tm, &time); tod_reg_val = time % 86400; day_reg_val = time / 86400; do { mask = BITFMASK(RTC_DAY); value = BITFVAL(RTC_DAY, day_reg_val); CHECK_ERROR(pmic_write_reg(REG_RTC_DAY, value, mask)); mask = BITFMASK(RTC_TIME); value = BITFVAL(RTC_TIME, tod_reg_val); CHECK_ERROR(pmic_write_reg(REG_RTC_TIME, value, mask)); mask = BITFMASK(RTC_DAY); CHECK_ERROR(pmic_read_reg(REG_RTC_DAY, &value, mask)); day_reg_val2 = BITFEXT(value, RTC_DAY); } while (day_reg_val != day_reg_val2); return 0; }
static int mc13892_regulator_init(struct mc13892 *mc13892) { unsigned int value; pmic_event_callback_t power_key_event; int register_mask; pr_info("Initializing regulators for MX53 EVK \n"); /* subscribe PWRON1 event to enable ON_OFF key */ power_key_event.param = NULL; power_key_event.func = (void *)power_on_evt_handler; pmic_event_subscribe(EVENT_PWRONI, power_key_event); /* Bit 4 DRM: keep VSRTC and CLK32KMCU on for all states */ #if defined(CONFIG_RTC_DRV_MXC_V2) || defined(CONFIG_RTC_DRV_MXC_V2_MODULE) value = BITFVAL(DRM, 1); register_mask = BITFMASK(DRM); pmic_write_reg(REG_POWER_CTL0, value, register_mask); #endif /* Set the STANDBYSECINV bit, so that STANDBY pin is * interpreted as active low. */ value = BITFVAL(STANDBYSECINV, 1); register_mask = BITFMASK(STANDBYSECINV); pmic_write_reg(REG_POWER_CTL2, value, register_mask); /* Disable coin cell charger since the cell is not rechargeable */ value = BITFVAL(COINCHEN, 0) | BITFVAL(VCOIN, VCOIN_3_0V); register_mask = BITFMASK(COINCHEN) | BITFMASK(VCOIN); pmic_write_reg(REG_POWER_CTL0, value, register_mask); mc13892_register_regulator(mc13892, MC13892_SW1, &sw1_init); mc13892_register_regulator(mc13892, MC13892_SW2, &sw2_init); mc13892_register_regulator(mc13892, MC13892_SW3, &sw3_init); mc13892_register_regulator(mc13892, MC13892_SW4, &sw4_init); mc13892_register_regulator(mc13892, MC13892_SWBST, &swbst_init); mc13892_register_regulator(mc13892, MC13892_VIOHI, &viohi_init); mc13892_register_regulator(mc13892, MC13892_VPLL, &vpll_init); mc13892_register_regulator(mc13892, MC13892_VDIG, &vdig_init); mc13892_register_regulator(mc13892, MC13892_VSD, &vsd_init); mc13892_register_regulator(mc13892, MC13892_VUSB2, &vusb2_init); mc13892_register_regulator(mc13892, MC13892_VVIDEO, &vvideo_init); mc13892_register_regulator(mc13892, MC13892_VAUDIO, &vaudio_init); mc13892_register_regulator(mc13892, MC13892_VCAM, &vcam_init); mc13892_register_regulator(mc13892, MC13892_VGEN1, &vgen1_init); mc13892_register_regulator(mc13892, MC13892_VGEN2, &vgen2_init); mc13892_register_regulator(mc13892, MC13892_VGEN3, &vgen3_init); mc13892_register_regulator(mc13892, MC13892_VUSB, &vusb_init); mc13892_register_regulator(mc13892, MC13892_GPO1, &gpo1_init); mc13892_register_regulator(mc13892, MC13892_GPO2, &gpo2_init); mc13892_register_regulator(mc13892, MC13892_GPO3, &gpo3_init); mc13892_register_regulator(mc13892, MC13892_GPO4, &gpo4_init); return 0; }
static int tps6518x_vcom_set_voltage(struct regulator_dev *reg, int minuV, int uV) { struct tps6518x *tps6518x = rdev_get_drvdata(reg); unsigned int cur_reg_val; /* current register value to modify */ unsigned int new_reg_val; /* new register value to write */ int retval; /* * this will not work on tps65182 */ if (tps6518x->revID == 65182) { //printk("%s %s %d RETURN ERROR 65182! \n",__FILE__,__func__,__LINE__); return 0; } ///del,compare for patch:TPS6518x-unable-to-set-VCOM.patch if ((-uV) < 200000) { //printk("%s %s %d too small return uV=%ld\n",__FILE__,__func__,__LINE__,uV); return 0; } //printk(" tps vcom uV=%ld \n",uV); switch (tps6518x->revID & 15) { case 0 : /* TPS65180 */ case 1 : /* TPS65181 */ case 4 : /* TPS65180-rev1 */ tps6518x_reg_read(REG_TPS65180_VCOM_ADJUST,&cur_reg_val); new_reg_val = to_reg_val(cur_reg_val, BITFMASK(VCOM_SET), BITFVAL(VCOM_SET, vcom_uV_to_rs(uV))); retval = tps6518x_reg_write(REG_TPS65180_VCOM_ADJUST, new_reg_val); break; case 5 : /* TPS65185 */ case 6 : /* TPS65186 */ retval = tps6518x_reg_write(REG_TPS65185_VCOM1, vcom2_uV_to_rs(uV) & 255); tps6518x_reg_read( REG_TPS65185_VCOM2,&cur_reg_val); new_reg_val = to_reg_val(cur_reg_val, BITFMASK(VCOM2_SET), BITFVAL(VCOM2_SET, vcom2_uV_to_rs(uV)/256)); retval = tps6518x_reg_write(REG_TPS65185_VCOM2, new_reg_val); break; default : retval = -1; } return retval; }
static int mc13892_vsd_set_voltage(struct regulator *reg, int uV) { unsigned int register_val = 0, register_mask = 0; unsigned int register1; int voltage, mV = uV / 1000; if ((mV >= 1800) && (mV < 2000)) voltage = VSD_1_8V; else if ((mV >= 2000) && (mV < 2600)) voltage = VSD_2_0V; else if ((mV >= 2600) && (mV < 2700)) voltage = VSD_2_6V; else if ((mV >= 2700) && (mV < 2800)) voltage = VSD_2_7V; else if ((mV >= 2800) && (mV < 2900)) voltage = VSD_2_8V; else if ((mV >= 2900) && (mV < 3000)) voltage = VSD_2_9V; else if ((mV >= 3000) && (mV < 3150)) voltage = VSD_3_0V; else voltage = VSD_3_15V; register_val = BITFVAL(VSD, voltage); register_mask = BITFMASK(VSD); register1 = REG_SETTING_1; return (pmic_write_reg(register1, register_val, register_mask)); }
static int max17135_vcom_enable(struct regulator_dev *reg) { struct max17135 *max17135 = rdev_get_drvdata(reg); /* * Check to see if we need to set the VCOM voltage. * Should only be done one time. And, we can * only change vcom voltage if we have been enabled. */ if (!max17135->vcom_setup && max17135_is_power_good(max17135)) { max17135_vcom_set_voltage(reg, max17135->vcom_uV, max17135->vcom_uV, NULL); max17135->vcom_setup = true; } /* enable VCOM regulator output */ if (max17135->pass_num == 1) gpio_set_value(max17135->gpio_pmic_vcom_ctrl, 1); else { unsigned int reg_val; max17135_reg_read(REG_MAX17135_ENABLE, ®_val); reg_val &= ~BITFMASK(VCOM_ENABLE); reg_val |= BITFVAL(VCOM_ENABLE, 1); /* shift to correct bit */ max17135_reg_write(REG_MAX17135_ENABLE, reg_val); } return 0; }
static int mc13892_vgen2_set_voltage(struct regulator *reg, int uV) { unsigned int register_val = 0, register_mask = 0; unsigned int register1; int voltage, mV = uV / 1000; if ((mV >= 1200) && (mV < 1500)) voltage = VGEN2_1_2V; else if ((mV >= 1500) && (mV < 1600)) voltage = VGEN2_1_5V; else if ((mV >= 1600) && (mV < 1800)) voltage = VGEN2_1_6V; else if ((mV >= 1800) && (mV < 2700)) voltage = VGEN2_1_8V; else if ((mV >= 2700) && (mV < 2800)) voltage = VGEN2_2_7V; else if ((mV >= 2800) && (mV < 2900)) voltage = VGEN2_2_8V; else if ((mV >= 2900) && (mV < 3000)) voltage = VGEN2_2_9V; else voltage = VGEN2_3_0V; register_val = BITFVAL(VGEN2, voltage); register_mask = BITFMASK(VGEN2); register1 = REG_SETTING_0; return (pmic_write_reg(register1, register_val, register_mask)); }
static int papyrus_vcom_enable(struct regulator_dev *reg) { struct papyrus *papyrus = rdev_get_drvdata(reg); struct i2c_client *client; unsigned int reg_val; /* * Check to see if we need to set the VCOM voltage. * We can only change vcom voltage if we have been enabled. * TEQ-1762 - Jack says we need to set VCOM on every power up */ if (gpio_get_value(papyrus->gpio_pmic_pwrgood)) { papyrus_vcom_set_voltage(reg, papyrus_vcom_cur_voltage, papyrus_vcom_cur_voltage); papyrus->vcom_setup = true; } /* enable VCOM regulator output */ client = papyrus->i2c_client; reg_val = i2c_smbus_read_byte_data(client, REG_PAPYRUS_ENABLE); reg_val &= ~BITFMASK(VCOM_ENABLE); reg_val |= BITFVAL(VCOM_ENABLE, 1); /* shift to correct bit */ i2c_smbus_write_byte_data(client, REG_PAPYRUS_ENABLE, reg_val); return 0; }
/*! * This function is used to start charging a battery. For different charger, * different voltage and current range are supported. \n * * * @param chgr Charger as defined in \b t_batt_charger. * @param c_voltage Charging voltage. * @param c_current Charging current. * * @return This function returns PMIC_SUCCESS if successful. */ PMIC_STATUS pmic_batt_enable_charger(t_batt_charger chgr, unsigned char c_voltage, unsigned char c_current) { unsigned int val, mask, reg; val = 0; mask = 0; reg = 0; if (suspend_flag == 1) { return PMIC_ERROR; } switch (chgr) { case BATT_MAIN_CHGR: val = BITFVAL(MC13783_BATT_DAC_DAC, c_current) | BITFVAL(MC13783_BATT_DAC_V_DAC, c_voltage); mask = BITFMASK(MC13783_BATT_DAC_DAC) | BITFMASK(MC13783_BATT_DAC_V_DAC); reg = REG_CHARGER; break; case BATT_CELL_CHGR: val = BITFVAL(MC13783_BATT_DAC_V_COIN, c_voltage) | BITFVAL(MC13783_BATT_DAC_COIN_CH_EN, MC13783_BATT_DAC_COIN_CH_EN_ENABLED); mask = BITFMASK(MC13783_BATT_DAC_V_COIN) | BITFMASK(MC13783_BATT_DAC_COIN_CH_EN); reg = REG_POWER_CONTROL_0; break; case BATT_TRCKLE_CHGR: val = BITFVAL(MC13783_BATT_DAC_TRCKLE, c_current); mask = BITFMASK(MC13783_BATT_DAC_TRCKLE); reg = REG_CHARGER; break; default: return PMIC_PARAMETER_ERROR; } CHECK_ERROR(pmic_write_reg(reg, val, mask)); return PMIC_SUCCESS; }
static int mc13892_regulator_init(struct mc13892 *mc13892) { unsigned int value, register_mask; printk("Initializing regulators for Sharp Netwalker.\n"); if (mxc_cpu_is_rev(CHIP_REV_2_0) < 0) sw2_init.constraints.state_mem.uV = 1100000; else if (mxc_cpu_is_rev(CHIP_REV_2_0) >= 1) { sw2_init.constraints.state_mem.uV = 1250000; sw1_init.constraints.state_mem.uV = 1000000; } /* Enable coin cell charger */ value = BITFVAL(CIONCHEN, 1) | BITFVAL(VCOIN, VCOIN_3_0V); register_mask = BITFMASK(CIONCHEN) | BITFMASK(VCOIN); pmic_write_reg(REG_POWER_CTL0, value, register_mask); #if defined(CONFIG_RTC_DRV_MXC_V2) || defined(CONFIG_RTC_DRV_MXC_V2_MODULE) value = BITFVAL(DRM, 1); register_mask = BITFMASK(DRM); pmic_write_reg(REG_POWER_CTL0, value, register_mask); #endif // mc13892_register_regulator(mc13892, MC13892_SW1, &sw1_init); // mc13892_register_regulator(mc13892, MC13892_SW2, &sw2_init); // mc13892_register_regulator(mc13892, MC13892_SW3, &sw3_init); // mc13892_register_regulator(mc13892, MC13892_SW4, &sw4_init); // mc13892_register_regulator(mc13892, MC13892_SWBST, &swbst_init); // mc13892_register_regulator(mc13892, MC13892_VIOHI, &viohi_init); // mc13892_register_regulator(mc13892, MC13892_VPLL, &vpll_init); // mc13892_register_regulator(mc13892, MC13892_VDIG, &vdig_init); // mc13892_register_regulator(mc13892, MC13892_VSD, &vsd_init); // mc13892_register_regulator(mc13892, MC13892_VUSB2, &vusb2_init); // mc13892_register_regulator(mc13892, MC13892_VVIDEO, &vvideo_init); mc13892_register_regulator(mc13892, MC13892_VAUDIO, &vaudio_init); // mc13892_register_regulator(mc13892, MC13892_VCAM, &vcam_init); // mc13892_register_regulator(mc13892, MC13892_VGEN1, &vgen1_init); // mc13892_register_regulator(mc13892, MC13892_VGEN2, &vgen2_init); // mc13892_register_regulator(mc13892, MC13892_VGEN3, &vgen3_init); mc13892_register_regulator(mc13892, MC13892_VUSB, &vusb_init); mc13892_register_regulator(mc13892, MC13892_GPO1, &gpo1_init); mc13892_register_regulator(mc13892, MC13892_GPO2, &gpo2_init); mc13892_register_regulator(mc13892, MC13892_GPO3, &gpo3_init); mc13892_register_regulator(mc13892, MC13892_GPO4, &gpo4_init); regulator_has_full_constraints(); return 0; }
/*! * This function enables End-of-Life comparator. * * @param typical Falling Edge Threshold threshold. * @verbatim BPDET UVDET LOBATL ____ _____ ___________ 0 2.6 UVDET + 0.2 1 2.6 UVDET + 0.3 2 2.6 UVDET + 0.4 3 2.6 UVDET + 0.5 * * @return This function returns PMIC_SUCCESS if successful. */ PMIC_STATUS pmic_batt_bp_enable_eol(t_bp_threshold typical) { unsigned int val, mask; if (suspend_flag == 1) return PMIC_ERROR; val = BITFVAL(MC13783_BATT_DAC_EOL_CMP_EN, MC13783_BATT_DAC_EOL_CMP_EN_ENABLE) | BITFVAL(MC13783_BATT_DAC_EOL_SEL, typical); mask = BITFMASK(MC13783_BATT_DAC_EOL_CMP_EN) | BITFMASK(MC13783_BATT_DAC_EOL_SEL); CHECK_ERROR(pmic_write_reg(REG_POWER_CONTROL_0, val, mask)); return PMIC_SUCCESS; }
/*! * This function set the real time clock of PMIC * * @param pmic_time value of date and time * * @return This function returns PMIC_SUCCESS if successful. */ PMIC_STATUS pmic_rtc_set_time(struct timeval *pmic_time) { unsigned int tod_reg_val = 0; unsigned int day_reg_val = 0; unsigned int mask, value; tod_reg_val = pmic_time->tv_sec % 86400; day_reg_val = pmic_time->tv_sec / 86400; mask = BITFMASK(MC13783_RTCTIME_TIME); value = BITFVAL(MC13783_RTCTIME_TIME, tod_reg_val); CHECK_ERROR(pmic_write_reg(REG_RTC_TIME, value, mask)); mask = BITFMASK(MC13783_RTCDAY_DAY); value = BITFVAL(MC13783_RTCDAY_DAY, day_reg_val); CHECK_ERROR(pmic_write_reg(REG_RTC_DAY, value, mask)); return PMIC_SUCCESS; }
static int mc13892_swbst_disable(struct regulator *reg) { unsigned int register_val = 0, register_mask = 0; unsigned int register1; register_val = BITFVAL(SWBST_EN, SWBST_EN_DISABLE); register_mask = BITFMASK(SWBST_EN); register1 = REG_SW_5; return (pmic_write_reg(register1, register_val, register_mask)); }
static int mc13892_vusb_disable(struct regulator *reg) { unsigned int register_val = 0, register_mask = 0; unsigned int register1; register_val = BITFVAL(VUSB_EN, VUSB_EN_DISABLE); register_mask = BITFMASK(VUSB_EN); register1 = REG_USB1; return (pmic_write_reg(register1, register_val, register_mask)); }
static int pmic_set_chg_current(unsigned short curr) { unsigned int mask; unsigned int value; value = BITFVAL(BIT_CHG_CURR, curr); mask = BITFMASK(BIT_CHG_CURR); CHECK_ERROR(pmic_write_reg(REG_CHARGE, value, mask)); return 0; }
static int mc13892_vusb2_enable(struct regulator *reg) { unsigned int register_val = 0, register_mask = 0; unsigned int register1; register_val = BITFVAL(VUSB2_EN, VUSB2_EN_ENABLE); register_mask = BITFMASK(VUSB2_EN); register1 = REG_MODE_0; return (pmic_write_reg(register1, register_val, register_mask)); }
static int mc13892_vvideo_disable(struct regulator *reg) { unsigned int register_val = 0, register_mask = 0; unsigned int register1; register_val = BITFVAL(VVIDEO_EN, VVIDEO_EN_DISABLE); register_mask = BITFMASK(VVIDEO_EN); register1 = REG_MODE_1; return (pmic_write_reg(register1, register_val, register_mask)); }
static int tps6518x_display_enable(struct regulator_dev *reg) { struct tps6518x *tps6518x = rdev_get_drvdata(reg); unsigned int cur_reg_val; /* current register value to modify */ unsigned int fld_mask; /* register mask for bitfield to modify */ unsigned int fld_val; /* new bitfield value to write */ unsigned int new_reg_val; /* new register value to write */ if (tps6518x->revID == 65182) { epdc_pwr0_enable(reg); } else { //printk("%s %s %d tps6518x->revID=%d \n",__FILE__,__func__,__LINE__,tps6518x->revID); /* enable display regulators */ cur_reg_val = tps65180_current_Enable_Register & 0x3f; fld_mask = BITFMASK(VDDH_EN) | BITFMASK(VPOS_EN) | BITFMASK(VEE_EN) | BITFMASK(VNEG_EN); fld_val = BITFVAL(VDDH_EN, true) | BITFVAL(VPOS_EN, true) | BITFVAL(VEE_EN, true) | BITFVAL(VNEG_EN, true) | BITFVAL(VCOM_EN, false); new_reg_val = tps65180_current_Enable_Register = to_reg_val(cur_reg_val, fld_mask, fld_val); tps6518x_reg_write(REG_TPS65180_ENABLE, new_reg_val); /* turn on display regulators */ cur_reg_val = tps65180_current_Enable_Register & 0x3f; fld_mask = BITFMASK(ACTIVE); fld_val = BITFVAL(ACTIVE, true); new_reg_val = tps65180_current_Enable_Register = to_reg_val(cur_reg_val, fld_mask, fld_val); tps6518x_reg_write(REG_TPS65180_ENABLE, new_reg_val); } return tps6518x_wait_power_good(tps6518x); }
/*! * This function sets the output controls. * It sets the FETOVRD and FETCTRL bits of mc13783 * * @param control type of control. * * @return This function returns 0 if successful. */ PMIC_STATUS pmic_batt_set_out_control(t_control control) { unsigned int val, mask; if (suspend_flag == 1) return PMIC_ERROR; switch (control) { case CONTROL_HARDWARE: val = BITFVAL(MC13783_BATT_DAC_FETOVRD_EN, 0) | BITFVAL(MC13783_BATT_DAC_FETCTRL_EN, 0); mask = BITFMASK(MC13783_BATT_DAC_FETOVRD_EN) | BITFMASK(MC13783_BATT_DAC_FETCTRL_EN); break; case CONTROL_BPFET_LOW: val = BITFVAL(MC13783_BATT_DAC_FETOVRD_EN, 1) | BITFVAL(MC13783_BATT_DAC_FETCTRL_EN, 0); mask = BITFMASK(MC13783_BATT_DAC_FETOVRD_EN) | BITFMASK(MC13783_BATT_DAC_FETCTRL_EN); break; case CONTROL_BPFET_HIGH: val = BITFVAL(MC13783_BATT_DAC_FETOVRD_EN, 1) | BITFVAL(MC13783_BATT_DAC_FETCTRL_EN, 1); mask = BITFMASK(MC13783_BATT_DAC_FETOVRD_EN) | BITFMASK(MC13783_BATT_DAC_FETCTRL_EN); break; default: return PMIC_PARAMETER_ERROR; } CHECK_ERROR(pmic_write_reg(REG_CHARGER, val, mask)); return PMIC_SUCCESS; }
static int tps6518x_v3p3_disable(struct regulator_dev *reg) { unsigned int cur_reg_val; /* current register value to modify */ unsigned int new_reg_val; /* new register value to write */ cur_reg_val = tps65180_current_Enable_Register & 0x20; new_reg_val = tps65180_current_Enable_Register = to_reg_val(cur_reg_val, BITFMASK(V3P3_SW_EN), BITFVAL(V3P3_SW_EN, false)); return tps6518x_reg_write(REG_TPS65180_ENABLE, new_reg_val); }
/*! * This function set the real time clock alarm of PMIC * * @param pmic_time value of date and time * * @return This function returns PMIC_SUCCESS if successful. */ PMIC_STATUS pmic_rtc_set_time_alarm(struct timeval *pmic_time) { unsigned int tod_reg_val = 0; unsigned int day_reg_val = 0; unsigned int mask, value; if (down_interruptible(&mutex) < 0) return ret; tod_reg_val = pmic_time->tv_sec % 86400; day_reg_val = pmic_time->tv_sec / 86400; mask = BITFMASK(MC13783_RTCALARM_TIME); value = BITFVAL(MC13783_RTCALARM_TIME, tod_reg_val); CHECK_ERROR(pmic_write_reg(REG_RTC_ALARM, value, mask)); mask = BITFMASK(MC13783_RTCALARM_DAY); value = BITFVAL(MC13783_RTCALARM_DAY, day_reg_val); CHECK_ERROR(pmic_write_reg(REG_RTC_DAY_ALARM, value, mask)); up(&mutex); return PMIC_SUCCESS; }
static int mc13892_regulator_init(struct mc13892 *mc13892) { unsigned int value; pmic_event_callback_t power_key_event; int register_mask; printk("Initializing regulators for 3-stack.\n"); if (mxc_cpu_is_rev(CHIP_REV_2_0) < 0) sw2_init.constraints.state_mem.uV = 1100000; /* subscribe PWRON1 event to enable ON_OFF key */ power_key_event.param = NULL; power_key_event.func = (void *)power_on_evt_handler; pmic_event_subscribe(EVENT_PWRONI, power_key_event); /* Bit 4 DRM: keep VSRTC and CLK32KMCU on for all states */ pmic_read_reg(REG_POWER_CTL0, &value, 0xffffff); value |= 0x000010; pmic_write_reg(REG_POWER_CTL0, value, 0xffffff); /* Set the STANDBYSECINV bit, so that STANDBY pin is * interpreted as active low. */ value = BITFVAL(STANDBYSECINV, 1); register_mask = BITFMASK(STANDBYSECINV); pmic_write_reg(REG_POWER_CTL2, value, register_mask); mc13892_register_regulator(mc13892, MC13892_SW1, &sw1_init); mc13892_register_regulator(mc13892, MC13892_SW2, &sw2_init); mc13892_register_regulator(mc13892, MC13892_SW3, &sw3_init); mc13892_register_regulator(mc13892, MC13892_SW4, &sw4_init); mc13892_register_regulator(mc13892, MC13892_SWBST, &swbst_init); mc13892_register_regulator(mc13892, MC13892_VIOHI, &viohi_init); mc13892_register_regulator(mc13892, MC13892_VPLL, &vpll_init); mc13892_register_regulator(mc13892, MC13892_VDIG, &vdig_init); mc13892_register_regulator(mc13892, MC13892_VSD, &vsd_init); mc13892_register_regulator(mc13892, MC13892_VUSB2, &vusb2_init); mc13892_register_regulator(mc13892, MC13892_VVIDEO, &vvideo_init); mc13892_register_regulator(mc13892, MC13892_VAUDIO, &vaudio_init); mc13892_register_regulator(mc13892, MC13892_VCAM, &vcam_init); mc13892_register_regulator(mc13892, MC13892_VGEN1, &vgen1_init); mc13892_register_regulator(mc13892, MC13892_VGEN2, &vgen2_init); mc13892_register_regulator(mc13892, MC13892_VGEN3, &vgen3_init); mc13892_register_regulator(mc13892, MC13892_VUSB, &vusb_init); mc13892_register_regulator(mc13892, MC13892_GPO1, &gpo1_init); mc13892_register_regulator(mc13892, MC13892_GPO2, &gpo2_init); mc13892_register_regulator(mc13892, MC13892_GPO3, &gpo3_init); mc13892_register_regulator(mc13892, MC13892_GPO4, &gpo4_init); return 0; }
/*! * This function sets reverse supply mode. * * @param enable If enable is ture, reverse supply mode is enable, * or otherwise, reverse supply mode is disabled. * * @return This function returns PMIC_SUCCESS if successful. */ PMIC_STATUS pmic_batt_set_reverse_supply(bool enable) { unsigned val, mask; if (suspend_flag == 1) return PMIC_ERROR; val = BITFVAL(MC13783_BATT_DAC_REVERSE_SUPPLY, enable); mask = BITFMASK(MC13783_BATT_DAC_REVERSE_SUPPLY); CHECK_ERROR(pmic_write_reg(REG_CHARGER, val, mask)); return PMIC_SUCCESS; }
/*! * This function sets a 5K pull down at CHRGRAW. * To be used in the dual path charging configuration. * * @param enable If enable is true, 5k pull down is * enable, or otherwise, disabled. * * @return This function returns PMIC_SUCCESS if successful. */ PMIC_STATUS pmic_batt_set_5k_pull(bool enable) { unsigned val, mask; if (suspend_flag == 1) return PMIC_ERROR; val = BITFVAL(MC13783_BATT_DAC_5K, enable); mask = BITFMASK(MC13783_BATT_DAC_5K); CHECK_ERROR(pmic_write_reg(REG_CHARGER, val, mask)); return PMIC_SUCCESS; }