static int __efuse_prog(int blk, u32 val)
{
u32 cfg0 = __raw_readl((void *)REG_EFUSE_CFG0);
if (blk < 0 || blk >= EFUSE_BLOCK_MAX) /* debug purpose */
goto out;
/* enable pgm mode and setup magic number before programming */
cfg0 |= BIT_PGM_EN;
__raw_writel(cfg0, (void *)REG_EFUSE_CFG0);
__raw_writel(BITS_MAGIC_NUMBER(efuse_magic),
(void *)REG_EFUSE_MAGIC_NUMBER);
__raw_writel(val, (void *)REG_EFUSE_DATA_WR);
__raw_writel(BITS_READ_WRITE_INDEX(blk),
(void *)REG_EFUSE_READ_WRITE_INDEX);
pr_debug("cfg0 %x\n", __raw_readl((void *)REG_EFUSE_CFG0));
__raw_writel(BIT_PG_START, (void *)REG_EFUSE_MODE_CTRL);
if (IS_ERR_VALUE(__efuse_wait_clear(BIT_PGM_BUSY)))
goto out;
out:
__raw_writel(0, (void *)REG_EFUSE_MAGIC_NUMBER);
cfg0 &= ~BIT_PGM_EN;
__raw_writel(cfg0, (void *)REG_EFUSE_CFG0);
return 0;
}
static u32 adie_efuse_read(int blk_index)
{
u32 val = 0;
pr_debug("adie efuse read %d\n", blk_index);
adie_efuse_lock();
__adie_efuse_power_on();
/* enable adie_efuse module clk and power before */
/* FIXME: set read timing, why 0x20 (default value)
sci_adi_raw_write(ANA_REG_EFUSE_RD_TIMING_CTRL,
BITS_EFUSE_RD_TIMING(0x20));
*/
sci_adi_raw_write(ANA_REG_EFUSE_BLOCK_INDEX,
BITS_READ_WRITE_INDEX(blk_index));
sci_adi_raw_write(ANA_REG_EFUSE_MODE_CTRL, BIT_RD_START);
if (IS_ERR_VALUE(__adie_efuse_wait_clear(BIT_READ_BUSY)))
goto out;
val = sci_adi_read(ANA_REG_EFUSE_DATA_RD);
/* FIXME: reverse the otp value */
val = BITS_EFUSE_DATA_RD(~val);
out:
__adie_efuse_power_off();
adie_efuse_unlock();
return val;
}
static u32 __efuse_read(int blk)
{
u32 val = 0;
/* enable efuse module clk and power before */
__raw_writel(BITS_READ_WRITE_INDEX(blk),
(void *)REG_EFUSE_READ_WRITE_INDEX);
__raw_writel(BIT_RD_START, (void *)REG_EFUSE_MODE_CTRL);
if (IS_ERR_VALUE(__efuse_wait_clear(BIT_READ_BUSY)))
goto out;
val = __raw_readl((void *)REG_EFUSE_DATA_RD);
out:
return val;
}
