/***************************************************************************//**
* @brief
* Restore BURTC to reset state
* @note
* Before accessing the BURTC, BURSTEN in RMU->CTRL must be cleared.
* LOCK will not be reset to default value, as this will disable access
* to core BURTC registers.
******************************************************************************/
void BURTC_Reset(void)
{
/* Verify RMU BURSTEN is disabled */
EFM_ASSERT((RMU->CTRL & RMU_CTRL_BURSTEN) == 0);
/* Restore all essential BURTC registers to default config */
BURTC->IEN = _BURTC_IEN_RESETVALUE;
/* Modification of LPMODE register requires sync with potential ongoing
* register updates in LF domain. */
BURTC_Sync(BURTC_SYNCBUSY_LPMODE);
BURTC->LPMODE = _BURTC_LPMODE_RESETVALUE;
BURTC->LFXOFDET = _BURTC_LFXOFDET_RESETVALUE;
/* Modification of COMP0 register requires sync with potential ongoing
* register updates in LF domain. */
BURTC_Sync(BURTC_SYNCBUSY_COMP0);
BURTC->COMP0 = _BURTC_COMP0_RESETVALUE;
BURTC->FREEZE = _BURTC_FREEZE_RESETVALUE;
/* We must wait for SYNCBUSY before resetting the CTRL register. */
BURTC_Sync(BURTC_SYNCBUSY_LPMODE | BURTC_SYNCBUSY_COMP0);
BURTC->CTRL = _BURTC_CTRL_RESETVALUE;
}
/***************************************************************************//**
* @brief Set BURTC compare channel
*
* @param[in] comp Compare channel index, must be 0 for Giant / Leopard Gecko
*
* @param[in] value New compare value
******************************************************************************/
void BURTC_CompareSet(unsigned int comp, uint32_t value)
{
(void) comp; /* Unused parameter when EFM_ASSERT is undefined. */
EFM_ASSERT(comp == 0);
/* Modification of COMP0 register requires sync with potential ongoing
* register updates in LF domain. */
BURTC_Sync(BURTC_SYNCBUSY_COMP0);
/* Configure compare channel 0 */
BURTC->COMP0 = value;
}
/***************************************************************************//**
* @brief Initialize BURTC
*
* @details
* Configures the BURTC peripheral.
*
* @note
* Before initialization, BURTC module must first be enabled by clearing the
* reset bit in the RMU, i.e.
* @verbatim
* RMU_ResetControl(rmuResetBU, false);
* @endverbatim
* Compare channel 0 must be configured outside this function, before
* initialization if enable is set to true. The counter will always be reset.
*
* @param[in] burtcInit
* Pointer to BURTC initialization structure
******************************************************************************/
void BURTC_Init(const BURTC_Init_TypeDef *burtcInit)
{
uint32_t ctrl;
uint32_t presc;
/* Check initializer structure integrity */
EFM_ASSERT(burtcInit != (BURTC_Init_TypeDef *) 0);
/* Clock divider must be between 1 and 128, really on the form 2^n */
EFM_ASSERT((burtcInit->clkDiv >= 1) && (burtcInit->clkDiv <= 128));
/* Ignored compare bits during low power operation must be less than 7 */
/* Note! Giant Gecko revision C errata, do NOT use LPCOMP=7 */
EFM_ASSERT(burtcInit->lowPowerComp <= 6);
/* You cannot enable the BURTC if mode is set to disabled */
EFM_ASSERT((burtcInit->enable == false) ||
((burtcInit->enable == true) && (burtcInit->mode != burtcModeDisable)));
/* Low power mode is only available with LFRCO or LFXO as clock source */
EFM_ASSERT((burtcInit->clkSel != burtcClkSelULFRCO) ||
((burtcInit->clkSel == burtcClkSelULFRCO) && (burtcInit->lowPowerMode == burtcLPDisable)));
/* Calculate prescaler value from clock divider input */
/* Note! If clock select (clkSel) is ULFRCO, a clock divisor (clkDiv) of
value 1 will select a 2kHz ULFRCO clock, while any other value will
select a 1kHz ULFRCO clock source. */
presc = BURTC_DivToLog2(burtcInit->clkDiv);
/* Make sure all registers are updated simultaneously */
if (burtcInit->enable)
{
BURTC_FreezeEnable(true);
}
/* Modification of LPMODE register requires sync with potential ongoing
* register updates in LF domain. */
BURTC_Sync(BURTC_SYNCBUSY_LPMODE);
/* Configure low power mode */
BURTC->LPMODE = (uint32_t) (burtcInit->lowPowerMode);
/* New configuration */
ctrl = ((BURTC_CTRL_RSTEN) |
(burtcInit->mode) |
(burtcInit->debugRun << _BURTC_CTRL_DEBUGRUN_SHIFT) |
(burtcInit->compare0Top << _BURTC_CTRL_COMP0TOP_SHIFT) |
(burtcInit->lowPowerComp << _BURTC_CTRL_LPCOMP_SHIFT) |
(presc << _BURTC_CTRL_PRESC_SHIFT) |
(burtcInit->clkSel) |
(burtcInit->timeStamp << _BURTC_CTRL_BUMODETSEN_SHIFT));
/* Clear interrupts */
BURTC_IntClear(0xFFFFFFFF);
/* Set new configuration */
BURTC->CTRL = ctrl;
/* Enable BURTC and counter */
if (burtcInit->enable)
{
/* To enable BURTC counter, we need to disable reset */
BURTC_Enable(true);
/* Clear freeze */
BURTC_FreezeEnable(false);
}
}
