int main(void) { int Status; Status = BramExample(BRAM_DEVICE_ID); if (Status != XST_SUCCESS ) { xil_printf("Bram Example Test FAILED.\r\n"); return XST_FAILURE; } xil_printf("Bram Example Test PASSED.\r\n"); return XST_SUCCESS; }
int main() { static XIntc intc; static XBram microblaze_3_local_memory_dlmb_bram_if_cntlr_Bram; static XBram microblaze_3_local_memory_ilmb_bram_if_cntlr_Bram; Xil_ICacheEnable(); Xil_DCacheEnable(); print("---Entering main---\n\r"); { int status; print("\r\n Running IntcSelfTestExample() for microblaze_3_axi_intc...\r\n"); status = IntcSelfTestExample(XPAR_MICROBLAZE_3_AXI_INTC_DEVICE_ID); if (status == 0) { print("IntcSelfTestExample PASSED\r\n"); } else { print("IntcSelfTestExample FAILED\r\n"); } } { int Status; Status = IntcInterruptSetup(&intc, XPAR_MICROBLAZE_3_AXI_INTC_DEVICE_ID); if (Status == 0) { print("Intc Interrupt Setup PASSED\r\n"); } else { print("Intc Interrupt Setup FAILED\r\n"); } } /* * Peripheral SelfTest will not be run for axi_uartlite_2 * because it has been selected as the STDOUT device */ { u32 status; print("\r\nRunning GpioOutputExample() for axi_gpio_5...\r\n"); status = GpioOutputExample(XPAR_AXI_GPIO_5_DEVICE_ID,1); if (status == 0) { print("GpioOutputExample PASSED.\r\n"); } else { print("GpioOutputExample FAILED.\r\n"); } } { int status; print("\r\nRunning Bram Example() for microblaze_3_local_memory_dlmb_bram_if_cntlr...\r\n"); status = BramExample(XPAR_MICROBLAZE_3_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_DEVICE_ID); if (status == 0) { xil_printf("Bram Example PASSED.\r\n"); } else { print("Bram Example FAILED.\r\n"); } } { int Status; Status = BramIntrExample(&intc, \ µblaze_3_local_memory_dlmb_bram_if_cntlr_Bram, \ XPAR_MICROBLAZE_3_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_DEVICE_ID, \ XPAR_MICROBLAZE_3_AXI_INTC_MICROBLAZE_3_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_INTERRUPT_INTR); if (Status == 0 ) { print("Bram Interrupt Test PASSED. \r\n"); } else { print("Bram Interrupt Test FAILED.\r\n"); } } { int status; print("\r\nRunning Bram Example() for microblaze_3_local_memory_ilmb_bram_if_cntlr...\r\n"); status = BramExample(XPAR_MICROBLAZE_3_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_DEVICE_ID); if (status == 0) { xil_printf("Bram Example PASSED.\r\n"); } else { print("Bram Example FAILED.\r\n"); } } { int Status; Status = BramIntrExample(&intc, \ µblaze_3_local_memory_ilmb_bram_if_cntlr_Bram, \ XPAR_MICROBLAZE_3_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_DEVICE_ID, \ XPAR_MICROBLAZE_3_AXI_INTC_MICROBLAZE_3_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_INTERRUPT_INTR); if (Status == 0 ) { print("Bram Interrupt Test PASSED. \r\n"); } else { print("Bram Interrupt Test FAILED.\r\n"); } } print("---Exiting main---\n\r"); Xil_DCacheDisable(); Xil_ICacheDisable(); return 0; }
int main() { static XIntc intc; static XBram microblaze_4_local_memory_dlmb_bram_if_cntlr_Bram; static XBram microblaze_4_local_memory_ilmb_bram_if_cntlr_Bram; Xil_ICacheEnable(); Xil_DCacheEnable(); { int status; status = IntcSelfTestExample(XPAR_MICROBLAZE_4_AXI_INTC_DEVICE_ID); } { int Status; Status = IntcInterruptSetup(&intc, XPAR_MICROBLAZE_4_AXI_INTC_DEVICE_ID); } { int status; status = GpioOutputExample(XPAR_AXI_GPIO_1_DEVICE_ID,1); } { int status; status = BramExample(XPAR_MICROBLAZE_4_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_DEVICE_ID); } { int Status; Status = BramIntrExample(&intc, \ µblaze_4_local_memory_dlmb_bram_if_cntlr_Bram, \ XPAR_MICROBLAZE_4_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_DEVICE_ID, \ XPAR_MICROBLAZE_4_AXI_INTC_MICROBLAZE_4_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_INTERRUPT_INTR); } { int status; status = BramExample(XPAR_MICROBLAZE_4_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_DEVICE_ID); } { int Status; Status = BramIntrExample(&intc, \ µblaze_4_local_memory_ilmb_bram_if_cntlr_Bram, \ XPAR_MICROBLAZE_4_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_DEVICE_ID, \ XPAR_MICROBLAZE_4_AXI_INTC_MICROBLAZE_4_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_INTERRUPT_INTR); } Xil_DCacheDisable(); Xil_ICacheDisable(); return 0; }