static void c_can_hw_raminit_ti(const struct c_can_priv *priv, bool enable) { u32 mask = CAN_RAMINIT_ALL_MASK(priv->instance); u32 ctrl; spin_lock(&raminit_lock); ctrl = readl(priv->raminit_ctrlreg); /* We clear the done and start bit first. The start bit is * looking at the 0 -> transition, but is not self clearing; * And we clear the init done bit as well. */ ctrl &= ~CAN_RAMINIT_START_MASK(priv->instance); ctrl |= CAN_RAMINIT_DONE_MASK(priv->instance); writel(ctrl, priv->raminit_ctrlreg); ctrl &= ~CAN_RAMINIT_DONE_MASK(priv->instance); c_can_hw_raminit_wait_ti(priv, ctrl, mask); if (enable) { /* Set start bit and wait for the done bit. */ ctrl |= CAN_RAMINIT_START_MASK(priv->instance); writel(ctrl, priv->raminit_ctrlreg); ctrl |= CAN_RAMINIT_DONE_MASK(priv->instance); c_can_hw_raminit_wait_ti(priv, ctrl, mask); } spin_unlock(&raminit_lock); }
static void c_can_hw_raminit(const struct c_can_priv *priv, bool enable) { u32 val; val = readl(priv->raminit_ctrlreg); if (enable) val |= CAN_RAMINIT_START_MASK(priv->instance); else val &= ~CAN_RAMINIT_START_MASK(priv->instance); writel(val, priv->raminit_ctrlreg); }