static int dump_ccci_reg()
{
int fd, i;
unsigned char *base;
unsigned int k;
fd = open(MEM_DEV_PATH, O_RDWR);
if (fd < 0) {
ALOGD("MEM_DEV_PATH open failed");
return 1;
}
base = (unsigned char *) mmap(NULL, 4096, PROT_READ | PROT_WRITE, MAP_SHARED, fd, CCIF_BASE);
if (base == MAP_FAILED) {
ALOGD("mmap failed");
return 1;
}
ALOGD("CCIF_CON (0x%p) = %X\n", CCIF_CON(base), *CCIF_CON(base));
ALOGD("CCIF_BUSY (0x%p) = %X\n", CCIF_BUSY(base), *CCIF_BUSY(base));
ALOGD("CCIF_START (0x%p) = %X\n", CCIF_START(base), *CCIF_START(base));
ALOGD("CCIF_RCHNUM (0x%p) = %X\n", CCIF_RCHNUM(base), *CCIF_RCHNUM(base));
munmap(base, CCIF_BASE);
close(fd);
return 0;
}
static int __ccif_v1_get_rx_ch(ccif_t* ccif)
{
while (CCIF_CON_ARB != ccci_read32(CCIF_CON(ccif->m_reg_base))){
ccci_write32(CCIF_CON(ccif->m_reg_base), CCIF_CON_ARB);
}
return ccci_read32(CCIF_RCHNUM(ccif->m_reg_base));
}
static int __ccif_v1_dump_reg(ccif_t* ccif, unsigned int buf[], int len)
{
int i,j;
volatile unsigned int *curr_ccif_smem_addr = (volatile unsigned int *)CCIF_TXCHDATA(ccif->m_reg_base);
CCCI_DBG_MSG(ccif->m_md_id, "cci", "[CCCI REG_INFO]\n");
CCCI_DBG_MSG(ccif->m_md_id, "cci", "CON(%lx)=%08X, BUSY(%lx)=%08x, START(%lx)=%08x, MRCHNUM(%lx)=%08x\n",
CCIF_CON(ccif->m_reg_base), ccci_read32(CCIF_CON(ccif->m_reg_base)),
CCIF_BUSY(ccif->m_reg_base), ccci_read32(CCIF_BUSY(ccif->m_reg_base)),
CCIF_START(ccif->m_reg_base), ccci_read32(CCIF_START(ccif->m_reg_base)),
MD_CCIF_RCHNUM(ccif->m_md_reg_base), ccci_read32(MD_CCIF_RCHNUM(ccif->m_md_reg_base)));
CCCI_DBG_MSG(ccif->m_md_id, "cci", "MCON(%lx)=%08X, MBUSY(%lx)=%08x, MSTART(%lx)=%08x, RCHNUM(%lx)=%08x\n",
MD_CCIF_CON(ccif->m_md_reg_base), ccci_read32(MD_CCIF_CON(ccif->m_md_reg_base)),
MD_CCIF_BUSY(ccif->m_md_reg_base), ccci_read32(MD_CCIF_BUSY(ccif->m_md_reg_base)),
MD_CCIF_START(ccif->m_md_reg_base), ccci_read32(MD_CCIF_START(ccif->m_md_reg_base)),
CCIF_RCHNUM(ccif->m_reg_base), ccci_read32(CCIF_RCHNUM(ccif->m_reg_base)));
for(i=0; i<16; i++){
CCCI_DBG_MSG(ccif->m_md_id, "cci", "%08X: %08X %08X %08X %08X\n", (unsigned int)curr_ccif_smem_addr, \
curr_ccif_smem_addr[0], curr_ccif_smem_addr[1],
curr_ccif_smem_addr[2], curr_ccif_smem_addr[3]);
curr_ccif_smem_addr+=4;
}
if(buf == NULL || len < (4*16+8)){
// Only dump by log
return 0;
}else{
j=0;
buf[j++] = ccci_read32(CCIF_CON(ccif->m_reg_base));
buf[j++] = ccci_read32(CCIF_BUSY(ccif->m_reg_base));
buf[j++] = ccci_read32(CCIF_START(ccif->m_reg_base));
buf[j++] = ccci_read32(MD_CCIF_RCHNUM(ccif->m_reg_base));
buf[j++] = ccci_read32(MD_CCIF_CON(ccif->m_reg_base));
buf[j++] = ccci_read32(MD_CCIF_BUSY(ccif->m_reg_base));
buf[j++] = ccci_read32(MD_CCIF_START(ccif->m_reg_base));
buf[j++] = ccci_read32(CCIF_RCHNUM(ccif->m_reg_base));
curr_ccif_smem_addr = (volatile unsigned int *)CCIF_TXCHDATA(ccif->m_reg_base);
for(i=0; i<4*16; i++)
buf[j++] = curr_ccif_smem_addr[i];
}
return j;
}
static int __ccif_v1_reset(ccif_t* ccif)
{
ccci_write32(CCIF_CON(ccif->m_reg_base), 1);
ccif->m_rx_idx = 0;
ccif->m_tx_idx = 0;
// ACK MD all channel
ccci_write32(CCIF_ACK(ccif->m_reg_base), 0xFF);
__ccif_v1_clear_sram(ccif);
return 0;
}
static int __ccif_v1_init(ccif_t* ccif)
{
//*CCIF_CON(ccif->m_reg_base) = 1;
ccci_write32(CCIF_CON(ccif->m_reg_base), CCIF_CON_ARB);
ccif->m_rx_idx = 0;
ccif->m_tx_idx = 0;
// ACK MD all channel
//*CCIF_ACK(ccif->m_reg_base) = 0xFF;
ccci_write32(CCIF_ACK(ccif->m_reg_base), 0xFF);
__ccif_v1_clear_sram(ccif);
return 0;
}
