void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color) { BUG_ON(enable_1510_mode); if (d->dma_dev_attr & IS_WORD_16) { u16 w; w = dma_read(CCR2(lch)); w &= ~0x03; switch (mode) { case OMAP_DMA_CONSTANT_FILL: w |= 0x01; break; case OMAP_DMA_TRANSPARENT_COPY: w |= 0x02; break; case OMAP_DMA_COLOR_DIS: break; default: BUG(); } dma_write(w, CCR2(lch)); w = dma_read(LCH_CTRL(lch)); w &= ~0x0f; /* Default is channel type 2D */ if (mode) { dma_write((u16)color, COLOR_L(lch)); dma_write((u16)(color >> 16), COLOR_U(lch)); w |= 1; /* Channel type G */ } dma_write(w, LCH_CTRL(lch)); } else {
void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color) { BUG_ON(omap_dma_in_1510_mode()); if (cpu_class_is_omap1()) { u16 w; w = dma_read(CCR2(lch)); w &= ~0x03; switch (mode) { case OMAP_DMA_CONSTANT_FILL: w |= 0x01; break; case OMAP_DMA_TRANSPARENT_COPY: w |= 0x02; break; case OMAP_DMA_COLOR_DIS: break; default: BUG(); } dma_write(w, CCR2(lch)); w = dma_read(LCH_CTRL(lch)); w &= ~0x0f; /* Default is channel type 2D */ if (mode) { dma_write((u16)color, COLOR_L(lch)); dma_write((u16)(color >> 16), COLOR_U(lch)); w |= 1; /* Channel type G */ } dma_write(w, LCH_CTRL(lch)); } if (cpu_class_is_omap2()) { u32 val; val = dma_read(CCR(lch)); val &= ~((1 << 17) | (1 << 16)); switch (mode) { case OMAP_DMA_CONSTANT_FILL: val |= 1 << 16; break; case OMAP_DMA_TRANSPARENT_COPY: val |= 1 << 17; break; case OMAP_DMA_COLOR_DIS: break; default: BUG(); } dma_write(val, CCR(lch)); color &= 0xffffff; dma_write(color, COLOR(lch)); } }
void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, int frame_count, int sync_mode, int dma_trigger, int src_or_dst_synch) { u32 l; l = dma_read(CSDP(lch)); l &= ~0x03; l |= data_type; dma_write(l, CSDP(lch)); if (cpu_class_is_omap1()) { u16 ccr; ccr = dma_read(CCR(lch)); ccr &= ~(1 << 5); if (sync_mode == OMAP_DMA_SYNC_FRAME) ccr |= 1 << 5; dma_write(ccr, CCR(lch)); ccr = dma_read(CCR2(lch)); ccr &= ~(1 << 2); if (sync_mode == OMAP_DMA_SYNC_BLOCK) ccr |= 1 << 2; dma_write(ccr, CCR2(lch)); } if (cpu_class_is_omap2() && dma_trigger) { u32 val; val = dma_read(CCR(lch)); /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */ val &= ~((3 << 19) | 0x1f); val |= (dma_trigger & ~0x1f) << 14; val |= dma_trigger & 0x1f; if (sync_mode & OMAP_DMA_SYNC_FRAME) val |= 1 << 5; else val &= ~(1 << 5); if (sync_mode & OMAP_DMA_SYNC_BLOCK) val |= 1 << 18; else val &= ~(1 << 18); if (src_or_dst_synch) val |= 1 << 24; /* source synch */ else val &= ~(1 << 24); /* dest synch */ dma_write(val, CCR(lch)); } dma_write(elem_count, CEN(lch)); dma_write(frame_count, CFN(lch)); }