static void
dec_3maxplus_ioasic_intr(void)
{
static bool warned = false;
bool ifound;
uint32_t imsk, intr, can_serve, xxxintr;
do {
ifound = false;
imsk = *(uint32_t *)(ioasic_base + IOASIC_IMSK);
intr = *(uint32_t *)(ioasic_base + IOASIC_INTR);
can_serve = intr & imsk;
CHECKINTR(SYS_DEV_SCC0, IOASIC_INTR_SCC_0);
CHECKINTR(SYS_DEV_SCC1, IOASIC_INTR_SCC_1);
CHECKINTR(SYS_DEV_LANCE, IOASIC_INTR_LANCE);
CHECKINTR(SYS_DEV_SCSI, IOASIC_INTR_SCSI);
CHECKINTR(SYS_DEV_OPT2, KN03_INTR_TC_2);
CHECKINTR(SYS_DEV_OPT1, KN03_INTR_TC_1);
CHECKINTR(SYS_DEV_OPT0, KN03_INTR_TC_0);
if (warned && !(can_serve & KN03_INTR_PSWARN)) {
printf("%s\n", "Power supply ok now.");
warned = false;
}
if ((can_serve & KN03_INTR_PSWARN) && (warned < 3)) {
warned = true;
printf("%s\n", "Power supply overheating");
}
#define ERRORS (IOASIC_INTR_SCSI_OVRUN|IOASIC_INTR_SCSI_READ_E|IOASIC_INTR_LANCE_READ_E)
#define PTRLOAD (IOASIC_INTR_SCSI_PTR_LOAD)
/*
* XXX future project is here XXX
* IOASIC DMA completion interrupt (PTR_LOAD) should be checked
* here, and DMA pointers serviced as soon as possible.
*/
/*
* All of IOASIC device interrupts comes through a single service
* request line coupled with MIPS CPU INT 0.
* Disabling INT 0 makes entire IOASIC interrupt services blocked,
* and it's harmful because it causes DMA overruns during network
* disk I/O interrupts.
* So, Non-DMA interrupts should be selectively disabled by masking
* IOASIC_IMSK register, and INT 3 itself be reenabled immediately,
* and made available all the time.
* DMA interrupts can then be serviced whilst still servicing
* non-DMA interrupts from ioctl devices or TC options.
*/
xxxintr = can_serve & (ERRORS | PTRLOAD);
if (xxxintr) {
ifound = true;
*(uint32_t *)(ioasic_base + IOASIC_INTR) = intr &~ xxxintr;
}
} while (ifound);
}
static void
dec_maxine_ioasic_intr(void)
{
bool ifound;
uint32_t imsk, intr, can_serve, xxxintr;
do {
ifound = false;
intr = *(uint32_t *)(ioasic_base + IOASIC_INTR);
imsk = *(uint32_t *)(ioasic_base + IOASIC_IMSK);
can_serve = intr & imsk;
CHECKINTR(SYS_DEV_DTOP, XINE_INTR_DTOP);
CHECKINTR(SYS_DEV_SCC0, IOASIC_INTR_SCC_0);
CHECKINTR(SYS_DEV_LANCE, IOASIC_INTR_LANCE);
CHECKINTR(SYS_DEV_SCSI, IOASIC_INTR_SCSI);
/* CHECKINTR(SYS_DEV_OPT2, XINE_INTR_VINT); */
CHECKINTR(SYS_DEV_ISDN, (IOASIC_INTR_ISDN_TXLOAD | IOASIC_INTR_ISDN_RXLOAD));
/* CHECKINTR(SYS_DEV_FDC, IOASIC_INTR_FDC); */
CHECKINTR(SYS_DEV_OPT1, XINE_INTR_TC_1);
CHECKINTR(SYS_DEV_OPT0, XINE_INTR_TC_0);
#define ERRORS (IOASIC_INTR_ISDN_OVRUN|IOASIC_INTR_SCSI_OVRUN|IOASIC_INTR_SCSI_READ_E|IOASIC_INTR_LANCE_READ_E)
#define PTRLOAD (IOASIC_INTR_ISDN_TXLOAD|IOASIC_INTR_ISDN_RXLOAD|IOASIC_INTR_SCSI_PTR_LOAD)
/*
* XXX future project is here XXX
* IOASIC DMA completion interrupt (PTR_LOAD) should be checked
* here, and DMA pointers serviced as soon as possible.
*/
/*
* All of IOASIC device interrupts comes through a single service
* request line coupled with MIPS CPU INT 3.
* Disabling INT 3 makes entire IOASIC interrupt services blocked,
* and it's harmful because it causes DMA overruns during network
* disk I/O interrupts.
* So, Non-DMA interrupts should be selectively disabled by masking
* IOASIC_IMSK register, and INT 3 itself be reenabled immediately,
* and made available all the time.
* DMA interrupts can then be serviced whilst still servicing
* non-DMA interrupts from ioctl devices or TC options.
*/
xxxintr = can_serve & (ERRORS | PTRLOAD);
if (xxxintr) {
ifound = true;
*(uint32_t *)(ioasic_base + IOASIC_INTR)
= intr &~ xxxintr;
}
} while (ifound);
}