void rm_audio_reset(void)
{
ulong flags;
DEFINE_SPINLOCK(lock);
spin_lock_irqsave(&lock, flags);
WRITE_MPEG_REG(PARSER_AUDIO_WP,
READ_MPEG_REG(AIU_MEM_AIFIFO_START_PTR));
WRITE_MPEG_REG(PARSER_AUDIO_RP,
READ_MPEG_REG(AIU_MEM_AIFIFO_START_PTR));
WRITE_MPEG_REG(PARSER_AUDIO_START_PTR,
READ_MPEG_REG(AIU_MEM_AIFIFO_START_PTR));
WRITE_MPEG_REG(PARSER_AUDIO_END_PTR,
READ_MPEG_REG(AIU_MEM_AIFIFO_END_PTR));
CLEAR_MPEG_REG_MASK(PARSER_ES_CONTROL, ES_AUD_MAN_RD_PTR);
WRITE_MPEG_REG(AIU_MEM_AIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
CLEAR_MPEG_REG_MASK(AIU_MEM_AIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
spin_unlock_irqrestore(&lock, flags);
return;
}
void esparser_audio_reset(struct stream_buf_s *buf)
{
ulong flags;
DEFINE_SPINLOCK(lock);
spin_lock_irqsave(&lock, flags);
WRITE_MPEG_REG(PARSER_AUDIO_WP,
READ_MPEG_REG(AIU_MEM_AIFIFO_START_PTR));
WRITE_MPEG_REG(PARSER_AUDIO_RP,
READ_MPEG_REG(AIU_MEM_AIFIFO_START_PTR));
WRITE_MPEG_REG(PARSER_AUDIO_START_PTR,
READ_MPEG_REG(AIU_MEM_AIFIFO_START_PTR));
WRITE_MPEG_REG(PARSER_AUDIO_END_PTR,
READ_MPEG_REG(AIU_MEM_AIFIFO_END_PTR));
CLEAR_MPEG_REG_MASK(PARSER_ES_CONTROL, ES_AUD_MAN_RD_PTR);
WRITE_MPEG_REG(AIU_MEM_AIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
CLEAR_MPEG_REG_MASK(AIU_MEM_AIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
buf->flag |= BUF_FLAG_PARSER;
audio_data_parsed = 0;
spin_unlock_irqrestore(&lock, flags);
return;
}
static void enable_dsp(int flag)
{
struct clk *clk;
int xtal = 0;
/* RESET DSP */
if(!flag)
CLEAR_MPEG_REG_MASK(AUD_ARC_CTL, 1);
/*write more for make the dsp is realy reset!*/
SET_MPEG_REG_MASK(RESET2_REGISTER, RESET_AUD_ARC);
// M1 has this bug also????
// SET_MPEG_REG_MASK(RESET2_REGISTER, RESET_AUD_ARC);
//SET_MPEG_REG_MASK(RESET2_REGISTER, RESET_AUD_ARC);
/* Enable BVCI low 16MB address mapping to DDR */
// SET_MPEG_REG_MASK(AUD_ARC_CTRL, (1<<DDR_CTL_MAPDDR));
/* polling highest bit of IREG_DDR_CTRL until the mapping is done */
if (flag) {
SET_MPEG_REG_MASK(AUD_ARC_CTL, 1);
CLEAR_MPEG_REG_MASK(AUD_ARC_CTL, 1);
clk=clk_get_sys("a9_clk", NULL);
if(!clk)
{
printk(KERN_ERR "can't find clk %s for a9_clk SETTING!\n\n","clk_xtal");
}
else
{
xtal=clk_get_rate(clk);
}
DSP_WD(DSP_ARM_REF_CLK_VAL, xtal);
}
}
void reset_dsp( struct audiodsp_priv *priv)
{
halt_dsp(priv);
//flush_and_inv_dcache_all();
/* map DSP 0 address so that reset vector points to same vector table as ARC1 */
CLEAR_MPEG_REG_MASK(AUD_ARC_CTL, (0xfff << 4));
// SET_MPEG_REG_MASK(SDRAM_CTL0,1);//arc mapping to ddr memory
SET_MPEG_REG_MASK(AUD_ARC_CTL, ((AUDIO_DSP_START_PHY_ADDR)>> 20) << 4);
// decode option
if(IEC958_mode_codec){
if(IEC958_mode_codec == 4){//dd+
DSP_WD(DSP_DECODE_OPTION, decopt|(3<<30));
}else{
DSP_WD(DSP_DECODE_OPTION, decopt|(1<<31));//dd,dts
}
}
else{
DSP_WD(DSP_DECODE_OPTION, decopt&(~(1<<31)));
}
printk("reset dsp : dec opt=%x\n", DSP_RD(DSP_DECODE_OPTION));
if(!priv->dsp_is_started){
DSP_PRNT("dsp reset now\n");
enable_dsp(1);
}
else{
dsp_mailbox_send(priv,1,M2B_IRQ0_DSP_WAKEUP,0,0,0);
DSP_WD(DSP_STATUS, DSP_STATUS_WAKEUP);
msleep(1);/*waiting arc625 run again */
}
return;
}
static int vid_transfer(logo_object_t *plogo)
{
amlog_mask_level(LOG_MASK_DEVICE,LOG_LEVEL_LOW,"start video transfer\n");;
SET_MPEG_REG_MASK(VPP_MISC, VPP_VD1_PREBLEND | VPP_PREBLEND_EN | VPP_VD1_POSTBLEND);
CLEAR_MPEG_REG_MASK(VPP_MISC, VPP_OSD1_POSTBLEND | VPP_OSD2_POSTBLEND);
return SUCCESS;
}
static void setup_vb(u32 addr, int s)
{
WRITE_MPEG_REG(VLD_MEM_VIFIFO_START_PTR, addr);
WRITE_MPEG_REG(VLD_MEM_VIFIFO_CURR_PTR, addr);
WRITE_MPEG_REG(VLD_MEM_VIFIFO_END_PTR, (addr + s + PADDINGSIZE + 7) & ~7);
SET_MPEG_REG_MASK(VLD_MEM_VIFIFO_CONTROL, MEM_BUFCTRL_INIT);
CLEAR_MPEG_REG_MASK(VLD_MEM_VIFIFO_CONTROL, MEM_BUFCTRL_INIT);
WRITE_MPEG_REG(VLD_MEM_VIFIFO_BUF_CNTL, MEM_BUFCTRL_MANUAL);
WRITE_MPEG_REG(VLD_MEM_VIFIFO_WP, addr);
SET_MPEG_REG_MASK(VLD_MEM_VIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
CLEAR_MPEG_REG_MASK(VLD_MEM_VIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
SET_MPEG_REG_MASK(VLD_MEM_VIFIFO_CONTROL, MEM_FILL_ON_LEVEL | MEM_CTRL_FILL_EN | MEM_CTRL_EMPTY_EN);
}
static int hardware_init(logo_object_t *plogo,int logo_size)
{
u32 *mc_addr_aligned = (u32 *)vmjpeg_mc;
int ret;
if(plogo->para.output_dev_type <=LOGO_DEV_VID ) //now only support display on video layer.
{
if(plogo->para.output_dev_type < LOGO_DEV_VID)
plogo->need_transfer=TRUE;
else
plogo->need_transfer=FALSE;
}
else
{
return -EINVAL;
}
WRITE_MPEG_REG(RESET0_REGISTER, RESET_VCPU | RESET_CCPU);
if (amvdec_loadmc(mc_addr_aligned) < 0) {
amlog_mask_level(LOG_MASK_PARSER,LOG_LEVEL_LOW,"[jpeglogo]: Can not loading HW decoding ucode.\n");
return -EBUSY;
}
amlog_mask_level(LOG_MASK_PARSER,LOG_LEVEL_LOW,"load micro code completed\n");
jpeglogo_prot_init(plogo);
ret= request_irq(INT_MAILBOX_1A, jpeglogo_isr,
IRQF_SHARED, "jpeglogo-irq", (void *)hardware_init);
if (ret) {
amlog_mask_level(LOG_MASK_PARSER,LOG_LEVEL_LOW,"jpeglogo_init irq register error.\n");
return -ENOENT;
}
amlog_mask_level(LOG_MASK_PARSER,LOG_LEVEL_LOW,"jpeg irq request ok\n");
setup_vb((u32)plogo->para.mem_addr,logo_size);
WRITE_MPEG_REG(M4_CONTROL_REG, 0x0300);
WRITE_MPEG_REG(POWER_CTL_VLD, 0);
SET_MPEG_REG_MASK(VPP_MISC,VPP_VD1_PREBLEND | VPP_VD1_POSTBLEND); //disable video layer.
CLEAR_MPEG_REG_MASK(VPP_MISC, VPP_OSD1_POSTBLEND | VPP_OSD2_POSTBLEND);
//set initial screen mode :
return SUCCESS;
}
s32 tsdemux_init(u32 vid, u32 aid, u32 sid, u32 pcrid, bool is_hevc)
{
s32 r;
u32 parser_sub_start_ptr;
u32 parser_sub_end_ptr;
u32 parser_sub_rp;
#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6
switch_mod_gate_by_type(MOD_DEMUX, 1);
#endif
parser_sub_start_ptr = READ_MPEG_REG(PARSER_SUB_START_PTR);
parser_sub_end_ptr = READ_MPEG_REG(PARSER_SUB_END_PTR);
parser_sub_rp = READ_MPEG_REG(PARSER_SUB_RP);
WRITE_MPEG_REG(RESET1_REGISTER, RESET_PARSER);
#ifdef ENABLE_DEMUX_DRIVER
tsdemux_reset();
#else
WRITE_MPEG_REG(RESET1_REGISTER, RESET_PARSER | RESET_DEMUXSTB);
WRITE_MPEG_REG(STB_TOP_CONFIG, 0);
WRITE_MPEG_REG(DEMUX_CONTROL, 0);
#endif
/* set PID filter */
printk("tsdemux video_pid = 0x%x, audio_pid = 0x%x, sub_pid = 0x%x, pcrid = 0x%x\n",
vid, aid, sid, pcr_pid);
#ifndef ENABLE_DEMUX_DRIVER
WRITE_MPEG_REG(FM_WR_DATA,
(((vid & 0x1fff) | (VIDEO_PACKET << 13)) << 16) |
((aid & 0x1fff) | (AUDIO_PACKET << 13)));
WRITE_MPEG_REG(FM_WR_ADDR, 0x8000);
while (READ_MPEG_REG(FM_WR_ADDR) & 0x8000) {
;
}
WRITE_MPEG_REG(FM_WR_DATA,
(((sid & 0x1fff) | (SUB_PACKET << 13)) << 16) | 0xffff);
WRITE_MPEG_REG(FM_WR_ADDR, 0x8001);
while (READ_MPEG_REG(FM_WR_ADDR) & 0x8000) {
;
}
WRITE_MPEG_REG(MAX_FM_COMP_ADDR, 1);
WRITE_MPEG_REG(STB_INT_MASK, 0);
WRITE_MPEG_REG(STB_INT_STATUS, 0xffff);
/* TS data path */
WRITE_MPEG_REG(FEC_INPUT_CONTROL, 0x7000);
WRITE_MPEG_REG(DEMUX_MEM_REQ_EN,
(1 << VIDEO_PACKET) |
(1 << AUDIO_PACKET) |
(1 << SUB_PACKET));
WRITE_MPEG_REG(DEMUX_ENDIAN,
(7 << OTHER_ENDIAN) |
(7 << BYPASS_ENDIAN) |
(0 << SECTION_ENDIAN));
WRITE_MPEG_REG(TS_HIU_CTL, 1 << USE_HI_BSF_INTERFACE);
WRITE_MPEG_REG(TS_FILE_CONFIG,
(demux_skipbyte << 16) |
(6 << DES_OUT_DLY) |
(3 << TRANSPORT_SCRAMBLING_CONTROL_ODD) |
(1 << TS_HIU_ENABLE) |
(4 << FEC_FILE_CLK_DIV));
/* enable TS demux */
WRITE_MPEG_REG(DEMUX_CONTROL, (1 << STB_DEMUX_ENABLE) | (1 << KEEP_DUPLICATE_PACKAGE));
#endif
if (fetchbuf == 0) {
printk("%s: no fetchbuf\n", __FUNCTION__);
return -ENOMEM;
}
/* hook stream buffer with PARSER */
#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
if (HAS_HEVC_VDEC && is_hevc) {
WRITE_MPEG_REG(PARSER_VIDEO_START_PTR,
READ_VREG(HEVC_STREAM_START_ADDR));
WRITE_MPEG_REG(PARSER_VIDEO_END_PTR,
READ_VREG(HEVC_STREAM_END_ADDR) - 8);
CLEAR_MPEG_REG_MASK(PARSER_ES_CONTROL, ES_VID_MAN_RD_PTR);
WRITE_VREG(DOS_GEN_CTRL0, 3<<1); // set vififo_vbuf_rp_sel=>hevc
SET_VREG_MASK(HEVC_STREAM_CONTROL, (1<<3)|(0<<4)); // set use_parser_vbuf_wp
SET_VREG_MASK(HEVC_STREAM_CONTROL, 1); // set stream_fetch_enable
SET_VREG_MASK(HEVC_STREAM_FIFO_CTL, (1<<29)); // set stream_buffer_hole with 256 bytes
} else
#endif
{
WRITE_MPEG_REG(PARSER_VIDEO_START_PTR,
READ_VREG(VLD_MEM_VIFIFO_START_PTR));
WRITE_MPEG_REG(PARSER_VIDEO_END_PTR,
READ_VREG(VLD_MEM_VIFIFO_END_PTR));
CLEAR_MPEG_REG_MASK(PARSER_ES_CONTROL, ES_VID_MAN_RD_PTR);
WRITE_VREG(VLD_MEM_VIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
CLEAR_VREG_MASK(VLD_MEM_VIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
if (HAS_HEVC_VDEC) {
WRITE_VREG(DOS_GEN_CTRL0, 0); // set vififo_vbuf_rp_sel=>vdec
}
}
WRITE_MPEG_REG(PARSER_AUDIO_START_PTR,
READ_MPEG_REG(AIU_MEM_AIFIFO_START_PTR));
WRITE_MPEG_REG(PARSER_AUDIO_END_PTR,
READ_MPEG_REG(AIU_MEM_AIFIFO_END_PTR));
CLEAR_MPEG_REG_MASK(PARSER_ES_CONTROL, ES_AUD_MAN_RD_PTR);
WRITE_MPEG_REG(PARSER_CONFIG,
(10 << PS_CFG_PFIFO_EMPTY_CNT_BIT) |
(1 << PS_CFG_MAX_ES_WR_CYCLE_BIT) |
(16 << PS_CFG_MAX_FETCH_CYCLE_BIT));
WRITE_MPEG_REG(AIU_MEM_AIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
CLEAR_MPEG_REG_MASK(AIU_MEM_AIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
WRITE_MPEG_REG(PARSER_SUB_START_PTR, parser_sub_start_ptr);
WRITE_MPEG_REG(PARSER_SUB_END_PTR, parser_sub_end_ptr);
WRITE_MPEG_REG(PARSER_SUB_RP, parser_sub_rp);
SET_MPEG_REG_MASK(PARSER_ES_CONTROL, (7 << ES_SUB_WR_ENDIAN_BIT) | ES_SUB_MAN_RD_PTR);
#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
if (HAS_HEVC_VDEC)
r = pts_start((is_hevc) ? PTS_TYPE_HEVC : PTS_TYPE_VIDEO);
else
#endif
r = pts_start(PTS_TYPE_VIDEO);
if (r < 0) {
printk("Video pts start failed.(%d)\n", r);
goto err1;
}
if ((r = pts_start(PTS_TYPE_AUDIO)) < 0) {
printk("Audio pts start failed.(%d)\n", r);
goto err2;
}
r = request_irq(INT_PARSER, parser_isr,
IRQF_SHARED, "tsdemux-fetch",
(void *)tsdemux_fetch_id);
if (r) {
goto err3;
}
WRITE_MPEG_REG(PARSER_INT_STATUS, 0xffff);
WRITE_MPEG_REG(PARSER_INT_ENABLE, PARSER_INTSTAT_FETCH_CMD << PARSER_INT_HOST_EN_BIT);
WRITE_MPEG_REG(PARSER_VIDEO_HOLE, 0x400);
WRITE_MPEG_REG(PARSER_AUDIO_HOLE, 0x400);
discontinued_counter = 0;
#ifndef ENABLE_DEMUX_DRIVER
r = request_irq(INT_DEMUX, tsdemux_isr,
IRQF_SHARED, "tsdemux-irq",
(void *)tsdemux_irq_id);
WRITE_MPEG_REG(STB_INT_MASK,
(1 << SUB_PES_READY)
| (1 << NEW_PDTS_READY)
| (1 << DIS_CONTINUITY_PACKET));
if (r) {
goto err4;
}
#else
tsdemux_config();
tsdemux_request_irq(tsdemux_isr, (void *)tsdemux_irq_id);
if (vid < 0x1FFF) {
curr_vid_id = vid;
tsdemux_set_vid(vid);
}
if (aid < 0x1FFF) {
curr_aud_id = aid;
tsdemux_set_aid(aid);
}
if (sid < 0x1FFF) {
curr_sub_id = sid;
tsdemux_set_sid(sid);
}
curr_pcr_id = pcr_pid;
if ((pcr_pid < 0x1FFF) && (pcr_pid != vid) && (pcr_pid != aid) && (pcr_pid != sid)) {
tsdemux_set_pcrid(pcr_pid);
}
#endif
reset_pcr_regs();
first_pcr = 0;
pcrscr_valid=1;
return 0;
#ifndef ENABLE_DEMUX_DRIVER
err4:
free_irq(INT_PARSER, (void *)tsdemux_fetch_id);
#endif
err3:
pts_stop(PTS_TYPE_AUDIO);
err2:
#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
if (HAS_HEVC_VDEC)
pts_stop((is_hevc) ? PTS_TYPE_HEVC : PTS_TYPE_VIDEO);
else
#endif
pts_stop(PTS_TYPE_VIDEO);
err1:
printk("TS Demux init failed.\n");
return -ENOENT;
}
s32 esparser_init(struct stream_buf_s *buf)
{
s32 r;
u32 pts_type;
u32 parser_sub_start_ptr;
u32 parser_sub_end_ptr;
u32 parser_sub_rp;
bool first_use = false;
#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
if (HAS_HEVC_VDEC && (buf->type == BUF_TYPE_HEVC)) {
pts_type = PTS_TYPE_HEVC;
} else
#endif
if (buf->type == BUF_TYPE_VIDEO) {
pts_type = PTS_TYPE_VIDEO;
} else if (buf->type & BUF_TYPE_AUDIO) {
pts_type = PTS_TYPE_AUDIO;
} else if (buf->type & BUF_TYPE_SUBTITLE) {
pts_type = PTS_TYPE_MAX;
} else {
return -EINVAL;
}
parser_sub_start_ptr = READ_MPEG_REG(PARSER_SUB_START_PTR);
parser_sub_end_ptr = READ_MPEG_REG(PARSER_SUB_END_PTR);
parser_sub_rp = READ_MPEG_REG(PARSER_SUB_RP);
buf->flag |= BUF_FLAG_PARSER;
if (atomic_add_return(1, &esparser_use_count) == 1) {
first_use = true;
if (fetchbuf == 0) {
printk("%s: no fetchbuf\n", __FUNCTION__);
r = -ENOMEM;
goto Err_1;
}
if (search_pattern == NULL) {
search_pattern = (unsigned char *)kcalloc(1, SEARCH_PATTERN_LEN, GFP_KERNEL);
if (search_pattern == NULL) {
printk("%s: no search_pattern\n", __FUNCTION__);
r = -ENOMEM;
goto Err_1;
}
/* build a fake start code to get parser interrupt */
search_pattern[0] = 0x00;
search_pattern[1] = 0x00;
search_pattern[2] = 0x01;
search_pattern[3] = 0xff;
search_pattern_map = dma_map_single(NULL, search_pattern,
SEARCH_PATTERN_LEN, DMA_TO_DEVICE);
}
/* reset PARSER with first esparser_init() call */
WRITE_MPEG_REG(RESET1_REGISTER, RESET_PARSER);
/* TS data path */
#ifndef CONFIG_AM_DVB
WRITE_MPEG_REG(FEC_INPUT_CONTROL, 0);
#else
tsdemux_set_reset_flag();
#endif
CLEAR_MPEG_REG_MASK(TS_HIU_CTL, 1 << USE_HI_BSF_INTERFACE);
CLEAR_MPEG_REG_MASK(TS_HIU_CTL_2, 1 << USE_HI_BSF_INTERFACE);
CLEAR_MPEG_REG_MASK(TS_HIU_CTL_3, 1 << USE_HI_BSF_INTERFACE);
CLEAR_MPEG_REG_MASK(TS_FILE_CONFIG, (1 << TS_HIU_ENABLE));
WRITE_MPEG_REG(PARSER_CONFIG,
(10 << PS_CFG_PFIFO_EMPTY_CNT_BIT) |
(1 << PS_CFG_MAX_ES_WR_CYCLE_BIT) |
(16 << PS_CFG_MAX_FETCH_CYCLE_BIT));
WRITE_MPEG_REG(PFIFO_RD_PTR, 0);
WRITE_MPEG_REG(PFIFO_WR_PTR, 0);
WRITE_MPEG_REG(PARSER_SEARCH_PATTERN, ES_START_CODE_PATTERN);
WRITE_MPEG_REG(PARSER_SEARCH_MASK, ES_START_CODE_MASK);
WRITE_MPEG_REG(PARSER_CONFIG,
(10 << PS_CFG_PFIFO_EMPTY_CNT_BIT) |
(1 << PS_CFG_MAX_ES_WR_CYCLE_BIT) |
PS_CFG_STARTCODE_WID_24 |
PS_CFG_PFIFO_ACCESS_WID_8 | /* single byte pop */
(16 << PS_CFG_MAX_FETCH_CYCLE_BIT));
WRITE_MPEG_REG(PARSER_CONTROL, PARSER_AUTOSEARCH);
tasklet_init(&esparser_tasklet, parser_tasklet, 0);
}
#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
/* hook stream buffer with PARSER */
if (HAS_HEVC_VDEC && (pts_type == PTS_TYPE_HEVC)) {
CLEAR_VREG_MASK(HEVC_STREAM_CONTROL, 1);
WRITE_MPEG_REG(PARSER_VIDEO_START_PTR,
READ_VREG(HEVC_STREAM_START_ADDR));
WRITE_MPEG_REG(PARSER_VIDEO_END_PTR,
READ_VREG(HEVC_STREAM_END_ADDR) - 8);
CLEAR_MPEG_REG_MASK(PARSER_ES_CONTROL, ES_VID_MAN_RD_PTR);
WRITE_VREG(DOS_GEN_CTRL0, 3<<1); // set vififo_vbuf_rp_sel=>hevc
SET_VREG_MASK(HEVC_STREAM_CONTROL, (1<<3)|(0<<4)); // set use_parser_vbuf_wp
SET_VREG_MASK(HEVC_STREAM_CONTROL, 1); // set stream_fetch_enable
SET_VREG_MASK(HEVC_STREAM_FIFO_CTL, (1<<29)); // set stream_buffer_hole with 256 bytes
video_data_parsed = 0;
} else
#endif
if (pts_type == PTS_TYPE_VIDEO) {
WRITE_MPEG_REG(PARSER_VIDEO_START_PTR,
READ_VREG(VLD_MEM_VIFIFO_START_PTR));
WRITE_MPEG_REG(PARSER_VIDEO_END_PTR,
READ_VREG(VLD_MEM_VIFIFO_END_PTR));
CLEAR_MPEG_REG_MASK(PARSER_ES_CONTROL, ES_VID_MAN_RD_PTR);
WRITE_VREG(VLD_MEM_VIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
CLEAR_VREG_MASK(VLD_MEM_VIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
if (HAS_HEVC_VDEC) {
WRITE_VREG(DOS_GEN_CTRL0, 0); // set vififo_vbuf_rp_sel=>vdec
}
video_data_parsed = 0;
} else if (pts_type == PTS_TYPE_AUDIO) {
WRITE_MPEG_REG(PARSER_AUDIO_START_PTR,
READ_MPEG_REG(AIU_MEM_AIFIFO_START_PTR));
WRITE_MPEG_REG(PARSER_AUDIO_END_PTR,
READ_MPEG_REG(AIU_MEM_AIFIFO_END_PTR));
CLEAR_MPEG_REG_MASK(PARSER_ES_CONTROL, ES_AUD_MAN_RD_PTR);
WRITE_MPEG_REG(AIU_MEM_AIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
CLEAR_MPEG_REG_MASK(AIU_MEM_AIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
audio_data_parsed = 0;
} else if (buf->type & BUF_TYPE_SUBTITLE) {
WRITE_MPEG_REG(PARSER_SUB_START_PTR, parser_sub_start_ptr);
WRITE_MPEG_REG(PARSER_SUB_END_PTR, parser_sub_end_ptr);
WRITE_MPEG_REG(PARSER_SUB_RP, parser_sub_rp);
SET_MPEG_REG_MASK(PARSER_ES_CONTROL, (7 << ES_SUB_WR_ENDIAN_BIT) | ES_SUB_MAN_RD_PTR);
}
if (pts_type < PTS_TYPE_MAX) {
r = pts_start(pts_type);
if (r < 0) {
printk("esparser_init: pts_start failed\n");
goto Err_1;
}
}
#if 0
if (buf->flag & BUF_FLAG_FIRST_TSTAMP) {
if (buf->type == BUF_TYPE_VIDEO) {
es_vpts_checkin(buf, buf->first_tstamp);
} else if (buf->type == BUF_TYPE_AUDIO) {
es_apts_checkin(buf, buf->first_tstamp);
}
buf->flag &= ~BUF_FLAG_FIRST_TSTAMP;
}
#endif
if (first_use) {
r = request_irq(INT_PARSER, parser_isr,
IRQF_SHARED, "esparser", (void *)esparser_id);
if (r) {
printk("esparser_init: irq register failed.\n");
goto Err_2;
}
WRITE_MPEG_REG(PARSER_INT_STATUS, 0xffff);
WRITE_MPEG_REG(PARSER_INT_ENABLE,
PARSER_INTSTAT_SC_FOUND << PARSER_INT_HOST_EN_BIT);
}
return 0;
Err_2:
pts_stop(pts_type);
Err_1:
atomic_dec(&esparser_use_count);
buf->flag &= ~BUF_FLAG_PARSER;
return r;
}
s32 rmparser_init(void)
{
s32 r;
parse_halt = 0;
if (fetchbuf == 0) {
printk("%s: no fetchbuf\n", __FUNCTION__);
return -ENOMEM;
}
WRITE_MPEG_REG(RESET1_REGISTER, RESET_PARSER);
/* TS data path */
/* Ignore FEC control for WetekPlay */
#ifndef CONFIG_WETEK
#ifndef CONFIG_AM_DVB
WRITE_MPEG_REG(FEC_INPUT_CONTROL, 0);
#else
tsdemux_set_reset_flag();
#endif
#endif
CLEAR_MPEG_REG_MASK(TS_HIU_CTL, 1 << USE_HI_BSF_INTERFACE);
CLEAR_MPEG_REG_MASK(TS_HIU_CTL_2, 1 << USE_HI_BSF_INTERFACE);
CLEAR_MPEG_REG_MASK(TS_HIU_CTL_3, 1 << USE_HI_BSF_INTERFACE);
CLEAR_MPEG_REG_MASK(TS_FILE_CONFIG, (1 << TS_HIU_ENABLE));
/* hook stream buffer with PARSER */
WRITE_MPEG_REG(PARSER_VIDEO_START_PTR,
READ_VREG(VLD_MEM_VIFIFO_START_PTR));
WRITE_MPEG_REG(PARSER_VIDEO_END_PTR,
READ_VREG(VLD_MEM_VIFIFO_END_PTR));
CLEAR_MPEG_REG_MASK(PARSER_ES_CONTROL, ES_VID_MAN_RD_PTR);
WRITE_MPEG_REG(PARSER_AUDIO_START_PTR,
READ_MPEG_REG(AIU_MEM_AIFIFO_START_PTR));
WRITE_MPEG_REG(PARSER_AUDIO_END_PTR,
READ_MPEG_REG(AIU_MEM_AIFIFO_END_PTR));
CLEAR_MPEG_REG_MASK(PARSER_ES_CONTROL, ES_AUD_MAN_RD_PTR);
WRITE_VREG(VLD_MEM_VIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
CLEAR_VREG_MASK(VLD_MEM_VIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
WRITE_MPEG_REG(AIU_MEM_AIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
CLEAR_MPEG_REG_MASK(AIU_MEM_AIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
WRITE_MPEG_REG(PFIFO_RD_PTR, 0);
WRITE_MPEG_REG(PFIFO_WR_PTR, 0);
WRITE_MPEG_REG(PARSER_SEARCH_MASK, 0);
WRITE_MPEG_REG(PARSER_CONTROL, (ES_SEARCH | ES_PARSER_START));
#ifdef MANAGE_PTS
if (pts_start(PTS_TYPE_VIDEO) < 0) {
goto Err_1;
}
if (pts_start(PTS_TYPE_AUDIO) < 0) {
goto Err_2;
}
#endif
/* enable interrupt */
r = request_irq(INT_PARSER, rm_parser_isr,
IRQF_SHARED, "rmparser", (void *)rmparser_id);
if (r) {
printk("RM parser irq register failed.\n");
goto Err_3;
}
WRITE_MPEG_REG(PARSER_INT_STATUS, 0xffff);
WRITE_MPEG_REG(PARSER_INT_ENABLE,
((PARSER_INT_ALL & (~PARSER_INTSTAT_FETCH_CMD)) << PARSER_INT_AMRISC_EN_BIT)
| (PARSER_INTSTAT_FETCH_CMD << PARSER_INT_HOST_EN_BIT));
return 0;
Err_3:
pts_stop(PTS_TYPE_AUDIO);
Err_2:
pts_stop(PTS_TYPE_VIDEO);
Err_1:
return -ENOENT;
}
static void amvdec_pg_enable(bool enable)
{
ulong timeout;
if (enable) {
CLK_GATE_ON(MDEC_CLK_PIC_DC);
CLK_GATE_ON(MDEC_CLK_DBLK);
CLK_GATE_ON(MC_CLK);
CLK_GATE_ON(IQIDCT_CLK);
//CLK_GATE_ON(VLD_CLK);
CLK_GATE_ON(AMRISC);
} else {
CLK_GATE_OFF(AMRISC);
timeout = jiffies + HZ / 10;
while (READ_MPEG_REG(MDEC_PIC_DC_STATUS) != 0) {
if (time_after(jiffies, timeout)) {
WRITE_MPEG_REG_BITS(MDEC_PIC_DC_CTRL, 1, 0, 1);
WRITE_MPEG_REG_BITS(MDEC_PIC_DC_CTRL, 0, 0, 1);
READ_MPEG_REG(MDEC_PIC_DC_STATUS);
READ_MPEG_REG(MDEC_PIC_DC_STATUS);
READ_MPEG_REG(MDEC_PIC_DC_STATUS);
break;
}
}
CLK_GATE_OFF(MDEC_CLK_PIC_DC);
timeout = jiffies + HZ / 10;
while (READ_MPEG_REG(DBLK_STATUS) & 1) {
if (time_after(jiffies, timeout)) {
WRITE_MPEG_REG(DBLK_CTRL, 3);
WRITE_MPEG_REG(DBLK_CTRL, 0);
READ_MPEG_REG(DBLK_STATUS);
READ_MPEG_REG(DBLK_STATUS);
READ_MPEG_REG(DBLK_STATUS);
break;
}
}
CLK_GATE_OFF(MDEC_CLK_DBLK);
timeout = jiffies + HZ / 10;
while (READ_MPEG_REG(MC_STATUS0) & 1) {
if (time_after(jiffies, timeout)) {
SET_MPEG_REG_MASK(MC_CTRL1, 0x9);
CLEAR_MPEG_REG_MASK(MC_CTRL1, 0x9);
READ_MPEG_REG(MC_STATUS0);
READ_MPEG_REG(MC_STATUS0);
READ_MPEG_REG(MC_STATUS0);
break;
}
}
CLK_GATE_OFF(MC_CLK);
timeout = jiffies + HZ / 10;
while (READ_MPEG_REG(DCAC_DMA_CTRL) & 0x8000) {
if (time_after(jiffies, timeout)) {
break;
}
}
WRITE_MPEG_REG(RESET0_REGISTER, 4);
READ_MPEG_REG(RESET0_REGISTER);
READ_MPEG_REG(RESET0_REGISTER);
READ_MPEG_REG(RESET0_REGISTER);
CLK_GATE_OFF(IQIDCT_CLK);
//CLK_GATE_OFF(VLD_CLK);
}
}
static inline void _init_tcon(tcon_conf_t *pConf)
{
set_lcd_gamma_table(pConf->GammaTableR, H_SEL_R);
set_lcd_gamma_table(pConf->GammaTableG, H_SEL_G);
set_lcd_gamma_table(pConf->GammaTableB, H_SEL_B);
WRITE_MPEG_REG(GAMMA_CNTL_PORT, pConf->gamma_cntl_port);
WRITE_MPEG_REG(GAMMA_VCOM_HSWITCH_ADDR, pConf->gamma_vcom_hswitch_addr);
WRITE_MPEG_REG(RGB_BASE_ADDR, pConf->rgb_base_addr);
WRITE_MPEG_REG(RGB_COEFF_ADDR, pConf->rgb_coeff_addr);
WRITE_MPEG_REG(POL_CNTL_ADDR, pConf->pol_cntl_addr);
WRITE_MPEG_REG(DITH_CNTL_ADDR, pConf->dith_cntl_addr);
WRITE_MPEG_REG(STH1_HS_ADDR, pConf->sth1_hs_addr);
WRITE_MPEG_REG(STH1_HE_ADDR, pConf->sth1_he_addr);
WRITE_MPEG_REG(STH1_VS_ADDR, pConf->sth1_vs_addr);
WRITE_MPEG_REG(STH1_VE_ADDR, pConf->sth1_ve_addr);
WRITE_MPEG_REG(STH2_HS_ADDR, pConf->sth2_hs_addr);
WRITE_MPEG_REG(STH2_HE_ADDR, pConf->sth2_he_addr);
WRITE_MPEG_REG(STH2_VS_ADDR, pConf->sth2_vs_addr);
WRITE_MPEG_REG(STH2_VE_ADDR, pConf->sth2_ve_addr);
WRITE_MPEG_REG(OEH_HS_ADDR, pConf->oeh_hs_addr);
WRITE_MPEG_REG(OEH_HE_ADDR, pConf->oeh_he_addr);
WRITE_MPEG_REG(OEH_VS_ADDR, pConf->oeh_vs_addr);
WRITE_MPEG_REG(OEH_VE_ADDR, pConf->oeh_ve_addr);
WRITE_MPEG_REG(VCOM_HSWITCH_ADDR, pConf->vcom_hswitch_addr);
WRITE_MPEG_REG(VCOM_VS_ADDR, pConf->vcom_vs_addr);
WRITE_MPEG_REG(VCOM_VE_ADDR, pConf->vcom_ve_addr);
WRITE_MPEG_REG(CPV1_HS_ADDR, pConf->cpv1_hs_addr);
WRITE_MPEG_REG(CPV1_HE_ADDR, pConf->cpv1_he_addr);
WRITE_MPEG_REG(CPV1_VS_ADDR, pConf->cpv1_vs_addr);
WRITE_MPEG_REG(CPV1_VE_ADDR, pConf->cpv1_ve_addr);
WRITE_MPEG_REG(CPV2_HS_ADDR, pConf->cpv2_hs_addr);
WRITE_MPEG_REG(CPV2_HE_ADDR, pConf->cpv2_he_addr);
WRITE_MPEG_REG(CPV2_VS_ADDR, pConf->cpv2_vs_addr);
WRITE_MPEG_REG(CPV2_VE_ADDR, pConf->cpv2_ve_addr);
WRITE_MPEG_REG(STV1_HS_ADDR, pConf->stv1_hs_addr);
WRITE_MPEG_REG(STV1_HE_ADDR, pConf->stv1_he_addr);
WRITE_MPEG_REG(STV1_VS_ADDR, pConf->stv1_vs_addr);
WRITE_MPEG_REG(STV1_VE_ADDR, pConf->stv1_ve_addr);
WRITE_MPEG_REG(STV2_HS_ADDR, pConf->stv2_hs_addr);
WRITE_MPEG_REG(STV2_HE_ADDR, pConf->stv2_he_addr);
WRITE_MPEG_REG(STV2_VS_ADDR, pConf->stv2_vs_addr);
WRITE_MPEG_REG(STV2_VE_ADDR, pConf->stv2_ve_addr);
WRITE_MPEG_REG(OEV1_HS_ADDR, pConf->oev1_hs_addr);
WRITE_MPEG_REG(OEV1_HE_ADDR, pConf->oev1_he_addr);
WRITE_MPEG_REG(OEV1_VS_ADDR, pConf->oev1_vs_addr);
WRITE_MPEG_REG(OEV1_VE_ADDR, pConf->oev1_ve_addr);
WRITE_MPEG_REG(OEV2_HS_ADDR, pConf->oev2_hs_addr);
WRITE_MPEG_REG(OEV2_HE_ADDR, pConf->oev2_he_addr);
WRITE_MPEG_REG(OEV2_VS_ADDR, pConf->oev2_vs_addr);
WRITE_MPEG_REG(OEV2_VE_ADDR, pConf->oev2_ve_addr);
WRITE_MPEG_REG(OEV3_HS_ADDR, pConf->oev3_hs_addr);
WRITE_MPEG_REG(OEV3_HE_ADDR, pConf->oev3_he_addr);
WRITE_MPEG_REG(OEV3_VS_ADDR, pConf->oev3_vs_addr);
WRITE_MPEG_REG(OEV3_VE_ADDR, pConf->oev3_ve_addr);
WRITE_MPEG_REG(INV_CNT_ADDR, pConf->inv_cnt_addr);
WRITE_MPEG_REG(TCON_MISC_SEL_ADDR, pConf->tcon_misc_sel_addr);
WRITE_MPEG_REG(DUAL_PORT_CNTL_ADDR, pConf->dual_port_cntl_addr);
CLEAR_MPEG_REG_MASK(VPP_MISC, VPP_OUT_SATURATE);
}
s32 tsdemux_init(u32 vid, u32 aid, u32 sid)
{
s32 r;
u32 parser_sub_start_ptr;
u32 parser_sub_end_ptr;
u32 parser_sub_rp;
parser_sub_start_ptr = READ_MPEG_REG(PARSER_SUB_START_PTR);
parser_sub_end_ptr = READ_MPEG_REG(PARSER_SUB_END_PTR);
parser_sub_rp = READ_MPEG_REG(PARSER_SUB_RP);
WRITE_MPEG_REG(RESET1_REGISTER, RESET_PARSER);
#ifdef ENABLE_DEMUX_DRIVER
tsdemux_reset();
#else
WRITE_MPEG_REG(RESET1_REGISTER, RESET_PARSER | RESET_DEMUXSTB);
WRITE_MPEG_REG(STB_TOP_CONFIG, 0);
WRITE_MPEG_REG(DEMUX_CONTROL, 0);
#endif
/* set PID filter */
printk("tsdemux video_pid = 0x%x, audio_pid = 0x%x, sub_pid = 0x%x\n",
vid, aid, sid);
#ifndef ENABLE_DEMUX_DRIVER
WRITE_MPEG_REG(FM_WR_DATA,
(((vid & 0x1fff) | (VIDEO_PACKET << 13)) << 16) |
((aid & 0x1fff) | (AUDIO_PACKET << 13)));
WRITE_MPEG_REG(FM_WR_ADDR, 0x8000);
while (READ_MPEG_REG(FM_WR_ADDR) & 0x8000) {
;
}
WRITE_MPEG_REG(FM_WR_DATA,
(((sid & 0x1fff) | (SUB_PACKET << 13)) << 16) | 0xffff);
WRITE_MPEG_REG(FM_WR_ADDR, 0x8001);
while (READ_MPEG_REG(FM_WR_ADDR) & 0x8000) {
;
}
WRITE_MPEG_REG(MAX_FM_COMP_ADDR, 1);
WRITE_MPEG_REG(STB_INT_MASK, 0);
WRITE_MPEG_REG(STB_INT_STATUS, 0xffff);
/* TS data path */
WRITE_MPEG_REG(FEC_INPUT_CONTROL, 0x7000);
WRITE_MPEG_REG(DEMUX_MEM_REQ_EN,
(1 << VIDEO_PACKET) |
(1 << AUDIO_PACKET) |
(1 << SUB_PACKET));
WRITE_MPEG_REG(DEMUX_ENDIAN,
(7 << OTHER_ENDIAN) |
(7 << BYPASS_ENDIAN) |
(0 << SECTION_ENDIAN));
WRITE_MPEG_REG(TS_HIU_CTL, 1 << USE_HI_BSF_INTERFACE);
WRITE_MPEG_REG(TS_FILE_CONFIG,
(demux_skipbyte << 16) |
(6 << DES_OUT_DLY) |
(3 << TRANSPORT_SCRAMBLING_CONTROL_ODD) |
(1 << TS_HIU_ENABLE) |
(4 << FEC_FILE_CLK_DIV));
/* enable TS demux */
WRITE_MPEG_REG(DEMUX_CONTROL, (1 << STB_DEMUX_ENABLE) | (1 << KEEP_DUPLICATE_PACKAGE));
#endif
if (fetchbuf == 0) {
printk("%s: no fetchbuf\n", __FUNCTION__);
return -ENOMEM;
}
/* hook stream buffer with PARSER */
WRITE_MPEG_REG(PARSER_VIDEO_START_PTR,
READ_MPEG_REG(VLD_MEM_VIFIFO_START_PTR));
WRITE_MPEG_REG(PARSER_VIDEO_END_PTR,
READ_MPEG_REG(VLD_MEM_VIFIFO_END_PTR));
CLEAR_MPEG_REG_MASK(PARSER_ES_CONTROL, ES_VID_MAN_RD_PTR);
WRITE_MPEG_REG(PARSER_AUDIO_START_PTR,
READ_MPEG_REG(AIU_MEM_AIFIFO_START_PTR));
WRITE_MPEG_REG(PARSER_AUDIO_END_PTR,
READ_MPEG_REG(AIU_MEM_AIFIFO_END_PTR));
CLEAR_MPEG_REG_MASK(PARSER_ES_CONTROL, ES_AUD_MAN_RD_PTR);
WRITE_MPEG_REG(PARSER_CONFIG,
(10 << PS_CFG_PFIFO_EMPTY_CNT_BIT) |
(1 << PS_CFG_MAX_ES_WR_CYCLE_BIT) |
(16 << PS_CFG_MAX_FETCH_CYCLE_BIT));
WRITE_MPEG_REG(VLD_MEM_VIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
CLEAR_MPEG_REG_MASK(VLD_MEM_VIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
WRITE_MPEG_REG(AIU_MEM_AIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
CLEAR_MPEG_REG_MASK(AIU_MEM_AIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
WRITE_MPEG_REG(PARSER_SUB_START_PTR, parser_sub_start_ptr);
WRITE_MPEG_REG(PARSER_SUB_END_PTR, parser_sub_end_ptr);
WRITE_MPEG_REG(PARSER_SUB_RP, parser_sub_rp);
SET_MPEG_REG_MASK(PARSER_ES_CONTROL, (7 << ES_SUB_WR_ENDIAN_BIT) | ES_SUB_MAN_RD_PTR);
if ((r = pts_start(PTS_TYPE_VIDEO)) < 0) {
printk("Video pts start failed.(%d)\n", r);
goto err1;
}
if ((r = pts_start(PTS_TYPE_AUDIO)) < 0) {
printk("Audio pts start failed.(%d)\n", r);
goto err2;
}
r = request_irq(INT_PARSER, parser_isr,
IRQF_SHARED, "tsdemux-fetch",
(void *)tsdemux_fetch_id);
if (r) {
goto err3;
}
WRITE_MPEG_REG(PARSER_INT_STATUS, 0xffff);
WRITE_MPEG_REG(PARSER_INT_ENABLE, PARSER_INTSTAT_FETCH_CMD << PARSER_INT_HOST_EN_BIT);
WRITE_MPEG_REG(PARSER_VIDEO_HOLE, 0x400);
WRITE_MPEG_REG(PARSER_AUDIO_HOLE, 0x400);
discontinued_counter = 0;
#ifndef ENABLE_DEMUX_DRIVER
r = request_irq(INT_DEMUX, tsdemux_isr,
IRQF_SHARED, "tsdemux-irq",
(void *)tsdemux_irq_id);
WRITE_MPEG_REG(STB_INT_MASK,
(1 << SUB_PES_READY)
| (1 << NEW_PDTS_READY)
| (1 << DIS_CONTINUITY_PACKET));
if (r) {
goto err4;
}
#else
tsdemux_config();
tsdemux_request_irq(tsdemux_isr, (void *)tsdemux_irq_id);
if (vid < 0x1FFF) {
tsdemux_set_vid(vid);
}
if (aid < 0x1FFF) {
tsdemux_set_aid(aid);
}
if (sid < 0x1FFF) {
tsdemux_set_sid(sid);
}
#endif
return 0;
#ifndef ENABLE_DEMUX_DRIVER
err4:
free_irq(INT_PARSER, (void *)tsdemux_fetch_id);
#endif
err3:
pts_stop(PTS_TYPE_AUDIO);
err2:
pts_stop(PTS_TYPE_VIDEO);
err1:
printk("TS Demux init failed.\n");
return -ENOENT;
}
