/*--------------------------------------------------------------------------*/ void SYS_Init(void) { /*---------------------------------------------------------------------------------------------------------*/ /* Init System Clock */ /*---------------------------------------------------------------------------------------------------------*/ /* Enable Internal RC 22.1184 MHz clock */ CLK_EnableXtalRC(CLK_PWRCON_OSC22M_EN_Msk); /* Waiting for Internal RC clock ready */ CLK_WaitClockReady(CLK_CLKSTATUS_OSC22M_STB_Msk); /* Switch HCLK clock source to Internal RC and HCLK source divide 1 */ CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC, CLK_CLKDIV_HCLK(1)); #if (!CRYSTAL_LESS) /* Enable external XTAL 12 MHz clock */ CLK_EnableXtalRC(CLK_PWRCON_XTL12M_EN_Msk); /* Waiting for external XTAL clock ready */ CLK_WaitClockReady(CLK_CLKSTATUS_XTL12M_STB_Msk); /* Set core clock */ CLK_SetCoreClock(72000000); /* Select module clock source */ CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_HIRC, CLK_CLKDIV_UART(1)); CLK_SetModuleClock(USBD_MODULE, CLK_CLKSEL0_USB_S_PLL, CLK_CLKDIV_USB(3)); #else /* Enable Internal RC 48MHz clock */ CLK_EnableXtalRC(CLK_PWRCON_OSC48M_EN_Msk); /* Waiting for Internal RC clock ready */ CLK_WaitClockReady(CLK_CLKSTATUS_OSC48M_STB_Msk); /* Select module clock source */ CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_HIRC, CLK_CLKDIV_UART(1)); CLK_SetModuleClock(USBD_MODULE, CLK_CLKSEL0_USB_S_RC48M, CLK_CLKDIV_USB(1)); #endif /* Enable module clock */ CLK_EnableModuleClock(UART0_MODULE); CLK_EnableModuleClock(USBD_MODULE); /*---------------------------------------------------------------------------------------------------------*/ /* Init I/O Multi-function */ /*---------------------------------------------------------------------------------------------------------*/ /* Set GPB multi-function pins for UART0 RXD and TXD, and Clock Output */ SYS->GPB_MFP &= ~(SYS_GPB_MFP_PB0_Msk | SYS_GPB_MFP_PB1_Msk | SYS_GPB_MFP_PB8_Msk); SYS->ALT_MFP &= ~SYS_ALT_MFP_PB8_Msk; SYS->GPB_MFP |= (SYS_GPB_MFP_PB0_UART0_RXD | SYS_GPB_MFP_PB1_UART0_TXD | SYS_GPB_MFP_PB8_CLKO); SYS->ALT_MFP |= SYS_ALT_MFP_PB8_CLKO; /* Enable CLKO (PB.8) for monitor HCLK. CLKO = HCLK/8 Hz*/ EnableCLKO((2 << CLK_CLKSEL2_FRQDIV_S_Pos), 2); }
void SYS_Init(void) { /*---------------------------------------------------------------------------------------------------------*/ /* Init System Clock */ /*---------------------------------------------------------------------------------------------------------*/ /* Enable Internal RC 22.1184MHz clock */ CLK_EnableXtalRC(CLK_PWRCON_OSC22M_EN_Msk); /* Waiting for Internal RC clock ready */ CLK_WaitClockReady(CLK_CLKSTATUS_OSC22M_STB_Msk); /* Switch HCLK clock source to Internal RC and HCLK source divide 1 */ CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC, CLK_CLKDIV_HCLK(1)); /* Enable external XTAL 12MHz clock */ CLK_EnableXtalRC(CLK_PWRCON_XTL12M_EN_Msk); /* Waiting for external XTAL clock ready */ CLK_WaitClockReady(CLK_CLKSTATUS_XTL12M_STB_Msk); /* Set core clock as PLL_CLOCK from PLL */ CLK_SetCoreClock(PLL_CLOCK); /* Enable UART module clock */ CLK_EnableModuleClock(UART0_MODULE); CLK_EnableModuleClock(UART1_MODULE); /* Select UART module clock source */ CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_HXT, CLK_CLKDIV_UART(1)); CLK_SetModuleClock(UART1_MODULE, CLK_CLKSEL1_UART_S_HXT, CLK_CLKDIV_UART(1)); /*---------------------------------------------------------------------------------------------------------*/ /* Init I/O Multi-function */ /*---------------------------------------------------------------------------------------------------------*/ /* Set GPB multi-function pins for UART0 RXD and TXD */ /* Set GPB multi-function pins for UART1 RXD, TXD, nRTS and nCTS */ SYS->GPB_MFP &= ~(SYS_GPB_MFP_PB0_Msk | SYS_GPB_MFP_PB1_Msk | SYS_GPB_MFP_PB4_Msk | SYS_GPB_MFP_PB5_Msk | SYS_GPB_MFP_PB6_Msk | SYS_GPB_MFP_PB7_Msk); SYS->GPB_MFP |= (SYS_GPB_MFP_PB0_UART0_RXD | SYS_GPB_MFP_PB1_UART0_TXD | SYS_GPB_MFP_PB4_UART1_RXD | SYS_GPB_MFP_PB5_UART1_TXD | SYS_GPB_MFP_PB6_UART1_nRTS | SYS_GPB_MFP_PB7_UART1_nCTS); SYS->ALT_MFP &= ~(SYS_ALT_MFP_PB6_Msk | SYS_ALT_MFP_PB7_Msk); SYS->ALT_MFP |= SYS_ALT_MFP_PB6_UART1_nRTS | SYS_ALT_MFP_PB7_UART1_nCTS; }
void SYS_Init(void) { /*---------------------------------------------------------------------------------------------------------*/ /* Init System Clock */ /*---------------------------------------------------------------------------------------------------------*/ /* Enable Internal RC 22.1184MHz clock */ CLK_EnableXtalRC(CLK_PWRCON_OSC22M_EN_Msk); /* Waiting for Internal RC clock ready */ CLK_WaitClockReady(CLK_CLKSTATUS_OSC22M_STB_Msk); /* Switch HCLK clock source to Internal RC and HCLK source divide 1 */ CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC, CLK_CLKDIV_HCLK(1)); /* Enable external XTAL 12MHz clock */ CLK_EnableXtalRC(CLK_PWRCON_XTL12M_EN_Msk); /* Waiting for external XTAL clock ready */ CLK_WaitClockReady(CLK_CLKSTATUS_XTL12M_STB_Msk); /* Set core clock as PLL_CLOCK from PLL */ CLK_SetCoreClock(PLL_CLOCK); /* Enable UART0 and UART1 module clock */ CLK_EnableModuleClock(UART0_MODULE); CLK_EnableModuleClock(UART1_MODULE); CLK_EnableModuleClock(TMR0_MODULE); /* Select UART0 and UART1 module clock source */ CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_HXT, CLK_CLKDIV_UART(1)); CLK_SetModuleClock(UART1_MODULE, CLK_CLKSEL1_UART_S_HXT, CLK_CLKDIV_UART(1)); CLK_SetModuleClock(TMR0_MODULE, CLK_CLKSEL1_TMR0_S_HXT, 0); /*---------------------------------------------------------------------------------------------------------*/ /* Init I/O Multi-function */ /*---------------------------------------------------------------------------------------------------------*/ /* Set P3 multi-function pins for UART0 RXD and TXD */ SYS->P3_MFP &= ~(SYS_MFP_P30_Msk | SYS_MFP_P31_Msk); SYS->P3_MFP |= (SYS_MFP_P30_RXD0 | SYS_MFP_P31_TXD0); /* Set P0 multi-function pins for UART1 RXD and TXD */ SYS->P0_MFP &= ~(SYS_MFP_P00_Msk | SYS_MFP_P01_Msk); SYS->P0_MFP |= (SYS_MFP_P00_TXD1 | SYS_MFP_P01_RXD1); }
void SYS_Init(void) { /*---------------------------------------------------------------------------------------------------------*/ /* Init System Clock */ /*---------------------------------------------------------------------------------------------------------*/ /* Enable Internal RC 22.1184MHz clock */ CLK_EnableXtalRC(CLK_PWRCON_OSC22M_EN_Msk); /* Waiting for Internal RC clock ready */ CLK_WaitClockReady(CLK_CLKSTATUS_OSC22M_STB_Msk); /* Switch HCLK clock source to Internal RC and HCLK source divide 1 */ CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC, CLK_CLKDIV_HCLK(1)); /* Enable external XTAL 12MHz clock */ CLK_EnableXtalRC(CLK_PWRCON_XTL12M_EN_Msk); /* Waiting for clock ready */ CLK_WaitClockReady(CLK_CLKSTATUS_XTL12M_STB_Msk); /* Set core clock as PLL_CLOCK from PLL */ CLK_SetCoreClock(PLL_CLOCK); /* Enable UART module clock */ CLK_EnableModuleClock(UART0_MODULE); /* Select UART module clock source */ CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_HXT, CLK_CLKDIV_UART(1)); /* Enable Timer 0~3 module clock */ CLK_EnableModuleClock(TMR0_MODULE); CLK_EnableModuleClock(TMR2_MODULE); CLK_EnableModuleClock(TMR3_MODULE); /* Select Timer 0~3 module clock source */ CLK_SetModuleClock(TMR0_MODULE, CLK_CLKSEL1_TMR0_S_HXT, NULL); CLK_SetModuleClock(TMR2_MODULE, CLK_CLKSEL1_TMR2_S_HCLK, NULL); CLK_SetModuleClock(TMR3_MODULE, CLK_CLKSEL1_TMR3_S_HXT, NULL); /*---------------------------------------------------------------------------------------------------------*/ /* Init I/O Multi-function */ /*---------------------------------------------------------------------------------------------------------*/ /* Set PB multi-function pins for UART0 RXD, TXD */ SYS->GPB_MFP &= ~(SYS_GPB_MFP_PB0_Msk | SYS_GPB_MFP_PB1_Msk); SYS->GPB_MFP |= (SYS_GPB_MFP_PB0_UART0_RXD | SYS_GPB_MFP_PB1_UART0_TXD); /* Set PB multi-function pins for TM0, TM2, TM3 and TM2_EXT */ SYS->GPB_MFP &= ~(SYS_GPB_MFP_PB8_Msk | SYS_GPB_MFP_PB10_Msk | SYS_GPB_MFP_PB11_Msk | SYS_GPB_MFP_PB2_Msk); SYS->GPB_MFP |= (SYS_GPB_MFP_PB8_TM0 | SYS_GPB_MFP_PB10_TM2 | SYS_GPB_MFP_PB11_TM3 | SYS_GPB_MFP_PB2_TM2_EXT); SYS->ALT_MFP &= ~( SYS_ALT_MFP_PB8_Msk | SYS_ALT_MFP_PB10_Msk | SYS_ALT_MFP_PB11_Msk | SYS_ALT_MFP_PB2_Msk); SYS->ALT_MFP |= (SYS_ALT_MFP_PB8_TM0 | SYS_ALT_MFP_PB10_TM2 |SYS_ALT_MFP_PB11_TM3 | SYS_ALT_MFP_PB2_TM2_EXT); SYS->ALT_MFP2 &= ~SYS_ALT_MFP2_PB2_TM2_Msk; SYS->ALT_MFP2 |= SYS_ALT_MFP2_PB2_TM2_EXT; }
void SYS_Init(void) { /*---------------------------------------------------------------------------------------------------------*/ /* Init System Clock */ /*---------------------------------------------------------------------------------------------------------*/ /* Enable Internal RC clock */ CLK_EnableXtalRC(CLK_PWRCON_OSC22M_EN_Msk); /* Waiting for IRC22M clock ready */ CLK_WaitClockReady(CLK_CLKSTATUS_OSC22M_STB_Msk); /* Switch HCLK clock source to Internal RC and HCLK source divide 1 */ CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC, CLK_CLKDIV_HCLK(1)); /* Enable external 12MHz XTAL, internal 22.1184MHz */ CLK_EnableXtalRC(CLK_PWRCON_XTL12M_EN_Msk | CLK_PWRCON_OSC22M_EN_Msk); /* Enable PLL and Set PLL frequency */ CLK_SetCoreClock(PLLCON_SETTING); /* Waiting for clock ready */ CLK_WaitClockReady(CLK_CLKSTATUS_PLL_STB_Msk | CLK_CLKSTATUS_XTL12M_STB_Msk | CLK_CLKSTATUS_OSC22M_STB_Msk); /* Switch HCLK clock source to PLL, STCLK to HCLK/2 */ CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_CLKDIV_HCLK(2)); /* Enable UART module clock */ CLK_EnableModuleClock(UART0_MODULE); /* Enable PWM module clock */ CLK_EnableModuleClock(PWM01_MODULE); CLK_EnableModuleClock(PWM23_MODULE); /* Select UART module clock source */ CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_HXT, CLK_CLKDIV_UART(1)); /* Select PWM module clock source */ CLK_SetModuleClock(PWM01_MODULE, CLK_CLKSEL1_PWM01_S_HXT, 0); CLK_SetModuleClock(PWM23_MODULE, CLK_CLKSEL1_PWM23_S_HXT, 0); /* Reset PWMA channel0~channel3 */ SYS_ResetModule(PWM03_RST); /* Update System Core Clock */ /* User can use SystemCoreClockUpdate() to calculate PllClock, SystemCoreClock and CycylesPerUs automatically. */ //SystemCoreClockUpdate(); PllClock = PLL_CLOCK; // PLL SystemCoreClock = PLL_CLOCK / 1; // HCLK CyclesPerUs = PLL_CLOCK / 1000000; // For SYS_SysTickDelay() /*---------------------------------------------------------------------------------------------------------*/ /* Init I/O Multi-function */ /*---------------------------------------------------------------------------------------------------------*/ /* Set P3 multi-function pins for UART0 RXD and TXD */ SYS->P3_MFP = SYS_MFP_P30_RXD0 | SYS_MFP_P31_TXD0; /* Set P2 multi-function pins for PWMA Channel0~3 */ SYS->P2_MFP = SYS_MFP_P20_PWM0 | SYS_MFP_P21_PWM1 | SYS_MFP_P22_PWM2 | SYS_MFP_P23_PWM3; }
void Time::initialize() { CLK_EnableModuleClock(TMR0_MODULE); CLK_SetModuleClock(TMR0_MODULE,CLK_CLKSEL1_TMR0_S_HCLK,CLK_CLKDIV_UART(1)); TIMER_Open(TIMER0, TIMER_PERIODIC_MODE, 1000000/TIMER_INTERRUPT_PERIOD_MICROSECONDS); TIMER_EnableInt(TIMER0); NVIC_EnableIRQ(TMR0_IRQn); NVIC_SetPriority(TMR0_IRQn, TIMER_IRQ_PRIORITY); TIMER_Start(TIMER0); /* Start counting */ }
void SYS_Init(void) { /*---------------------------------------------------------------------------------------------------------*/ /* Init System Clock */ /*---------------------------------------------------------------------------------------------------------*/ /* Unlock protected registers */ SYS_UnlockReg(); /* Set P5 multi-function pins for XTAL1 and XTAL2 */ SYS->P5_MFP &= ~(SYS_MFP_P50_Msk | SYS_MFP_P51_Msk); SYS->P5_MFP |= (SYS_MFP_P50_XT1_IN | SYS_MFP_P51_XT1_OUT); /* Enable external 12MHz XTAL (UART), HIRC */ CLK->PWRCTL = CLK_PWRCTL_XTL12M | CLK_PWRCTL_HIRCEN_Msk; /* Waiting for clock ready */ CLK_WaitClockReady(CLK_STATUS_XTLSTB_Msk | CLK_STATUS_HIRCSTB_Msk); /* Switch HCLK clock source to XTL */ CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_XTAL,CLK_CLKDIV_HCLK(1)); /* Enable IP clock */ CLK->APBCLK = CLK_APBCLK_UART0CKEN_Msk | CLK_APBCLK_ADCCKEN_Msk | CLK_APBCLK_PWMCH01CKEN_Msk; /* Select UART clock source from external crystal */ CLK->CLKSEL1 = (CLK->CLKSEL1 & ~CLK_CLKSEL1_UARTSEL_Msk) | CLK_CLKSEL1_UARTSEL_XTAL; /* Select ADC clock source from external crystal */ CLK->CLKSEL1 = (CLK->CLKSEL1 & ~CLK_CLKSEL1_ADCSEL_Msk) | CLK_CLKSEL1_ADCSEL_XTAL; /* Select IP clock source */ CLK_SetModuleClock(UART0_MODULE,CLK_CLKSEL1_UARTSEL_XTAL,CLK_CLKDIV_UART(1)); CLK_SetModuleClock(ADC_MODULE,CLK_CLKSEL1_ADCSEL_XTAL,CLK_CLKDIV_ADC(6)); /* Update System Core Clock */ /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock and CycylesPerUs automatically. */ SystemCoreClockUpdate(); /*---------------------------------------------------------------------------------------------------------*/ /* Init I/O Multi-function */ /*---------------------------------------------------------------------------------------------------------*/ /* Set P1 multi-function pins for UART RXD, TXD and ADC channel 5 input */ SYS->P1_MFP = SYS_MFP_P12_UART0_RXD | SYS_MFP_P13_UART0_TXD | SYS_MFP_P15_ADC_CH5; /* Analog pin OFFD to prevent leakage */ P1->DINOFF |= (1 << 5) << GP_DINOFF_DINOFF0_Pos; /* Set P2 multi-function pins for PWM Channel 0. */ SYS->P2_MFP = SYS_MFP_P22_PWM0_CH0; /* Lock protected registers */ SYS_LockReg(); }
void SYS_Init(void) { /*---------------------------------------------------------------------------------------------------------*/ /* Init System Clock */ /*---------------------------------------------------------------------------------------------------------*/ /* Unlock protected registers */ SYS_UnlockReg(); /* Enable HIRC clock (Internal RC 22.1184MHz) */ CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk); /* Wait for HIRC clock ready */ CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); /* Select HCLK clock source as HIRC and and HCLK source divider as 1 */ CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV_HCLK(1)); /* Set P5 multi-function pins for crystal output/input */ SYS->P5_MFP &= ~(SYS_MFP_P50_Msk | SYS_MFP_P51_Msk); SYS->P5_MFP |= (SYS_MFP_P50_XT1_IN | SYS_MFP_P51_XT1_OUT); /* Enable HXT clock (external XTAL 12MHz) */ CLK_EnableXtalRC(CLK_PWRCTL_XTLEN_HXT); /* Wait for HXT clock ready */ CLK_WaitClockReady(CLK_STATUS_XTLSTB_Msk); /* Set core clock as PLL_CLOCK from PLL */ CLK_SetCoreClock(PLL_CLOCK); /* Enable UART module clock */ CLK_EnableModuleClock(UART0_MODULE); /* Select UART module clock source as HXT and UART module clock divider as 1 */ CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_XTAL, CLK_CLKDIV_UART(1)); /* Lock protected registers */ SYS_LockReg(); /*---------------------------------------------------------------------------------------------------------*/ /* Init I/O Multi-function */ /*---------------------------------------------------------------------------------------------------------*/ /* Set P0 multi-function pins for UART RXD and TXD */ SYS->P1_MFP &= ~(SYS_MFP_P12_Msk | SYS_MFP_P13_Msk); SYS->P1_MFP |= (SYS_MFP_P12_UART0_RXD | SYS_MFP_P13_UART0_TXD); //SYS->P0_MFP &= ~(SYS_MFP_P01_Msk | SYS_MFP_P00_Msk); //SYS->P0_MFP |= (SYS_MFP_P01_UART0_RXD | SYS_MFP_P00_UART0_TXD); /* Set P3 multi-function pins for Clock Output */ SYS->P3_MFP = SYS_MFP_P36_CLKO; }
void initialize() { IO::pinMode(MUX_ADR0_PIN, OUTPUT); IO::pinMode(MUX_ADR1_PIN, OUTPUT); IO::pinMode(MUX_ADR2_PIN, OUTPUT); IO::pinMode(V_IN_PIN, ANALOG_INPUT); IO::pinMode(OUTPUT_VOLTAGE_MINUS_PIN, ANALOG_INPUT); IO::pinMode(SMPS_CURRENT_PIN, ANALOG_INPUT); IO::pinMode(OUTPUT_VOLTAGE_PLUS_PIN, ANALOG_INPUT); IO::pinMode(DISCHARGE_CURRENT_PIN, ANALOG_INPUT); IO::pinMode(MUX0_Z_D_PIN, ANALOG_INPUT_DISCHARGE); IO::digitalWrite(MUX0_Z_D_PIN, 0); //initialize internal temperature sensor SYS->TEMPCR |= 1; //initialize TIMER 1 (mux ADC capacitor discharge) CLK_EnableModuleClock(TMR1_MODULE); CLK_SetModuleClock(TMR1_MODULE,CLK_CLKSEL1_TMR1_S_HCLK,CLK_CLKDIV_UART(1)); //TODO: 50kHz ?? TIMER_Open(TIMER1, TIMER_ONESHOT_MODE, 1000000 / ADC_CAPACITOR_DISCHARGE_DELAY_US); TIMER_EnableInt(TIMER1); NVIC_EnableIRQ(TMR1_IRQn); NVIC_SetPriority(TMR1_IRQn, ADC_C_DISCHARGE_IRQ_PRIORITY); //initialize ADC //init clock CLK_EnableModuleClock(ADC_MODULE); CLK_SetModuleClock(ADC_MODULE, CLK_CLKSEL1_ADC_S_HCLK, CLK_CLKDIV_ADC(CLK_GetHCLKFreq()/ADC_CLOCK_FREQUENCY)); //__HXT/ADC_CLOCK_FREQUENCY)); /* Set the ADC operation mode as burst, input mode as single-end and enable the analog input channel 2 */ ADC_Open(ADC, ADC_ADCR_DIFFEN_SINGLE_END, ADC_ADCR_ADMD_BURST, 0x1 << 2); ADC_SET_DMOF(ADC, ADC_ADCR_DMOF_UNSIGNED_OUTPUT); /* Power on ADC module */ ADC_POWER_ON(ADC); /* clear the A/D interrupt flag for safe */ ADC_CLR_INT_FLAG(ADC, ADC_ADF_INT); /* Enable the ADC interrupt */ ADC_EnableInt(ADC, ADC_ADF_INT); NVIC_EnableIRQ(ADC_IRQn); NVIC_SetPriority(ADC_IRQn, ADC_IRQ_PRIORITY); current_input_ = 0; startConversion(); }
void SYS_Init(void) { /*---------------------------------------------------------------------------------------------------------*/ /* Init System Clock */ /*---------------------------------------------------------------------------------------------------------*/ /* Enable Internal RC 22.1184 MHz clock */ CLK_EnableXtalRC(CLK_PWRCON_OSC22M_EN_Msk); /* Waiting for Internal RC clock ready */ CLK_WaitClockReady(CLK_CLKSTATUS_OSC22M_STB_Msk); /* Enable external 12 MHz XTAL */ CLK_EnableXtalRC(CLK_PWRCON_XTL12M_EN_Msk); /* Waiting for clock ready */ CLK_WaitClockReady(CLK_CLKSTATUS_XTL12M_STB_Msk); /* Set core clock rate as 72 MHz from PLL */ CLK_SetCoreClock(72000000); /* Select HXT as the clock source of UART0 */ CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_HXT, CLK_CLKDIV_UART(1)); /* Select HCLK as the clock source of SPI0 */ CLK_SetModuleClock(SPI0_MODULE, CLK_CLKSEL1_SPI0_S_HCLK, MODULE_NoMsk); /* Enable UART peripheral clock */ CLK_EnableModuleClock(UART0_MODULE); /* Enable SPI0 peripheral clock */ CLK_EnableModuleClock(SPI0_MODULE); /* Update System Core Clock */ /* User can use SystemCoreClockUpdate() to calculate PllClock, SystemCoreClock and CyclesPerUs automatically. */ SystemCoreClockUpdate(); /*---------------------------------------------------------------------------------------------------------*/ /* Init I/O Multi-function */ /*---------------------------------------------------------------------------------------------------------*/ /* Set PB multi-function pins for UART0 RXD and TXD */ SYS->GPB_MFP &= ~(SYS_GPB_MFP_PB0_Msk | SYS_GPB_MFP_PB1_Msk); SYS->GPB_MFP |= (SYS_GPB_MFP_PB0_UART0_RXD | SYS_GPB_MFP_PB1_UART0_TXD); /* Setup SPI0 multi-function pins */ SYS->GPC_MFP &= ~(SYS_GPC_MFP_PC0_Msk | SYS_GPC_MFP_PC1_Msk | SYS_GPC_MFP_PC2_Msk | SYS_GPC_MFP_PC3_Msk); SYS->GPC_MFP |= SYS_GPC_MFP_PC0_SPI0_SS0 | SYS_GPC_MFP_PC1_SPI0_CLK | SYS_GPC_MFP_PC2_SPI0_MISO0 | SYS_GPC_MFP_PC3_SPI0_MOSI0; SYS->ALT_MFP &= ~(SYS_ALT_MFP_PC0_Msk | SYS_ALT_MFP_PC1_Msk | SYS_ALT_MFP_PC2_Msk | SYS_ALT_MFP_PC3_Msk); SYS->ALT_MFP |= SYS_ALT_MFP_PC0_SPI0_SS0 | SYS_ALT_MFP_PC1_SPI0_CLK | SYS_ALT_MFP_PC2_SPI0_MISO0 | SYS_ALT_MFP_PC3_SPI0_MOSI0; }
void SYS_Init(void) { /* Unlock protected registers */ SYS_UnlockReg(); /*---------------------------------------------------------------------------------------------------------*/ /* Init System Clock */ /*---------------------------------------------------------------------------------------------------------*/ /* Set P5 multi-function pins for XTAL1 and XTAL2 */ SYS->P5_MFP &= ~(SYS_MFP_P50_Msk | SYS_MFP_P51_Msk); SYS->P5_MFP |= (SYS_MFP_P50_XTAL1 | SYS_MFP_P51_XTAL2); /* Enable external 12MHz XTAL, internal 22.1184MHz */ CLK_EnableXtalRC(CLK_PWRCON_HXT|CLK_PWRCON_HIRC_EN_Msk); /* Waiting for clock ready */ CLK_WaitClockReady(CLK_CLKSTATUS_XTL_STB_Msk | CLK_CLKSTATUS_IRC22M_STB_Msk); /* Switch HCLK clock source to XTL */ CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_XTAL,CLK_CLKDIV_HCLK(1)); /* STCLK to XTL STCLK to XTL */ CLK_SetSysTickClockSrc(CLK_CLKSEL0_STCLK_S_XTAL); /* Enable IP clock */ CLK_EnableModuleClock(UART_MODULE); CLK_EnableModuleClock(I2C_MODULE); /* Select IP clock source */ CLK_SetModuleClock(UART_MODULE,CLK_CLKSEL1_UART_S_XTAL,CLK_CLKDIV_UART(1)); /*---------------------------------------------------------------------------------------------------------*/ /* Init I/O Multi-function */ /*---------------------------------------------------------------------------------------------------------*/ /* Set P0 multi-function pins for UART RXD and TXD */ SYS->P0_MFP &= ~(SYS_MFP_P01_Msk | SYS_MFP_P00_Msk); SYS->P0_MFP |= (SYS_MFP_P01_RXD | SYS_MFP_P00_TXD); /* Lock protected registers */ SYS_LockReg(); /* Update System Core Clock */ SystemCoreClockUpdate(); }
void setupUART() { /* Enable peripheral clock */ CLK_EnableModuleClock(UART_MODULE); /* Peripheral clock source */ CLK_SetModuleClock(UART_MODULE, CLK_CLKSEL1_UART_S_HIRC, CLK_CLKDIV_UART(1)); /* Set PD multi-function pins for UART0 RXD, TXD */ SYS->P1_MFP &= ~(SYS_MFP_P12_Msk | SYS_MFP_P13_Msk); SYS->P1_MFP |= (SYS_MFP_P12_RXD | SYS_MFP_P13_TXD); //SYS->P0_MFP = SYS_MFP_P00_TXD | SYS_MFP_P01_RXD; /* Reset UART module */ SYS_ResetModule(UART_RST); /* Configure UART0 and set UART0 Baudrate */ UART_Open(UART0, 115200); }
void SYS_Init(void) { /*---------------------------------------------------------------------------------------------------------*/ /* Init System Clock */ /*---------------------------------------------------------------------------------------------------------*/ /* Enable Internal RC 22.1184MHz clock */ CLK_EnableXtalRC(CLK_PWRCON_OSC22M_EN_Msk); /* Waiting for Internal RC clock ready */ CLK_WaitClockReady(CLK_CLKSTATUS_OSC22M_STB_Msk); /* Switch HCLK clock source to Internal RC and HCLK source divide 1 */ CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC, CLK_CLKDIV_HCLK(1)); /* Enable external XTAL 12MHz clock and internal 10 kHz */ CLK_EnableXtalRC((CLK_PWRCON_XTL12M_EN_Msk | CLK_PWRCON_OSC10K_EN_Msk)); /* Waiting for clock ready */ CLK_WaitClockReady((CLK_CLKSTATUS_XTL12M_STB_Msk | CLK_CLKSTATUS_OSC10K_STB_Msk)); /* Set core clock as PLL_CLOCK from PLL */ CLK_SetCoreClock(PLL_CLOCK); /* Enable UART module clock */ CLK_EnableModuleClock(UART0_MODULE); /* Select UART module clock source */ CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_HXT, CLK_CLKDIV_UART(1)); /* Enable WDT module clock */ CLK_EnableModuleClock(WDT_MODULE); /* Select WDT module clock source */ CLK_SetModuleClock(WDT_MODULE, CLK_CLKSEL1_WDT_S_LIRC, NULL); /*---------------------------------------------------------------------------------------------------------*/ /* Init I/O Multi-function */ /*---------------------------------------------------------------------------------------------------------*/ /* Set PB multi-function pins for UART0 RXD, TXD */ SYS->GPB_MFP &= ~(SYS_GPB_MFP_PB0_Msk | SYS_GPB_MFP_PB1_Msk); SYS->GPB_MFP |= (SYS_GPB_MFP_PB0_UART0_RXD | SYS_GPB_MFP_PB1_UART0_TXD); }
void SYS_Init(void) { /* Unlock protected registers */ SYS_UnlockReg(); /* Set P5 multi-function pins for XTAL1 and XTAL2 */ SYS->P5_MFP &= ~(SYS_MFP_P50_Msk | SYS_MFP_P51_Msk); SYS->P5_MFP |= (SYS_MFP_P50_XT1_IN | SYS_MFP_P51_XT1_OUT); /* Enable external 12MHz XTAL (UART), and HIRC */ CLK->PWRCTL = CLK_PWRCTL_XTL12M | CLK_PWRCTL_HIRCEN_Msk; /* Waiting for clock ready */ CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk | CLK_STATUS_XTLSTB_Msk); /* Switch HCLK clock source to XTL */ CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_XTAL, CLK_CLKDIV_HCLK(1)); /* STCLK to XTL STCLK to XTL */ CLK_SetSysTickClockSrc(CLK_CLKSEL0_STCLKSEL_XTAL); /* Enable IP clock */ CLK_EnableModuleClock(UART0_MODULE); /* Select IP clock source */ CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_XTAL, CLK_CLKDIV_UART(1)); /*---------------------------------------------------------------------------------------------------------*/ /* Init I/O Multi-function */ /*---------------------------------------------------------------------------------------------------------*/ /* Set P1 multi-function pins for UART RXD, TXD */ SYS->P1_MFP = SYS_MFP_P12_UART0_RXD | SYS_MFP_P13_UART0_TXD; /* To update the variable SystemCoreClock */ SystemCoreClockUpdate(); /* Lock protected registers */ SYS_LockReg(); }
void SYS_Init(void) { /*---------------------------------------------------------------------------------------------------------*/ /* Init System Clock */ /*---------------------------------------------------------------------------------------------------------*/ /* Enable HIRC clock */ CLK_EnableXtalRC(CLK_PWRCON_IRC22M_EN_Msk); /* Waiting for HIRC clock ready */ CLK_WaitClockReady(CLK_CLKSTATUS_IRC22M_STB_Msk); /* Switch HCLK clock source to HIRC */ CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC, CLK_CLKDIV_HCLK(1)); /* Enable HXT and LIRC */ CLK_EnableXtalRC(CLK_PWRCON_XTL12M_EN_Msk | CLK_PWRCON_IRC10K_EN_Msk); /* Waiting for clock ready */ CLK_WaitClockReady(CLK_CLKSTATUS_XTL12M_STB_Msk | CLK_CLKSTATUS_IRC10K_STB_Msk); /* Set core clock as PLL_CLOCK from PLL and SysTick source to HCLK/2*/ CLK_SetCoreClock(PLL_CLOCK); CLK_SetSysTickClockSrc(CLK_CLKSEL0_STCLK_S_HCLK_DIV2); /* Enable peripheral clock */ CLK_EnableModuleClock(UART0_MODULE); CLK_EnableModuleClock(WDT_MODULE); /* Peripheral clock source */ CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_PLL, CLK_CLKDIV_UART(1)); CLK_SetModuleClock(WDT_MODULE, CLK_CLKSEL1_WDT_S_LIRC, 0); /*---------------------------------------------------------------------------------------------------------*/ /* Init I/O Multi-function */ /*---------------------------------------------------------------------------------------------------------*/ /* Set PB multi-function pins for UART0 RXD, TXD */ SYS->GPB_MFP &= ~(SYS_GPB_MFP_PB0_Msk | SYS_GPB_MFP_PB1_Msk); SYS->GPB_MFP |= (SYS_GPB_MFP_PB0_UART0_RXD | SYS_GPB_MFP_PB1_UART0_TXD); }
void SYS_Init(void) { /*---------------------------------------------------------------------------------------------------------*/ /* Init System Clock */ /*---------------------------------------------------------------------------------------------------------*/ /* Enable Internal RC clock */ CLK_EnableXtalRC(CLK_PWRCON_OSC22M_EN_Msk); /* Waiting for IRC22M clock ready */ CLK_WaitClockReady(CLK_CLKSTATUS_OSC22M_STB_Msk); /* Switch HCLK clock source to Internal RC and HCLK source divide 1 */ CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC, CLK_CLKDIV_HCLK(1)); /* Enable external 12MHz XTAL, internal 22.1184MHz */ CLK_EnableXtalRC(CLK_PWRCON_XTL12M_EN_Msk | CLK_PWRCON_OSC22M_EN_Msk); /* Enable PLL and Set PLL frequency */ CLK_SetCoreClock(PLL_CLOCK); /* Waiting for clock ready */ CLK_WaitClockReady(CLK_CLKSTATUS_PLL_STB_Msk | CLK_CLKSTATUS_XTL12M_STB_Msk | CLK_CLKSTATUS_OSC22M_STB_Msk); /* Switch HCLK clock source to PLL, STCLK to HCLK/2 */ CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_CLKDIV_HCLK(2)); /* Enable UART module clock */ CLK_EnableModuleClock(UART0_MODULE); /* Select UART module clock source */ CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_HXT, CLK_CLKDIV_UART(1)); /* Enable PWM0 clock source */ CLK_EnableModuleClock(PWM0_MODULE); /* Select PWM module clock source */ //CLK_SetModuleClock(PWM0_MODULE, CLK_CLKSEL3_PWM0_S_HClK, 0); CLK_SetModuleClock(PWM0_MODULE, CLK_CLKSEL3_PWM0_S_PLL, 0); /* Reset PWM0 */ SYS_ResetModule(PWM0_RST); /* Update System Core Clock */ /* User can use SystemCoreClockUpdate() to calculate PllClock, SystemCoreClock and CycylesPerUs automatically. */ //SystemCoreClockUpdate(); PllClock = PLL_CLOCK; // PLL SystemCoreClock = PLL_CLOCK / 1; // HCLK CyclesPerUs = PLL_CLOCK / 1000000; // For SYS_SysTickDelay() /*---------------------------------------------------------------------------------------------------------*/ /* Init I/O Multi-function */ /*---------------------------------------------------------------------------------------------------------*/ /* Set GPB multi-function pins for UART0 RXD and TXD */ SYS->GPB_MFP &= ~(SYS_GPB_MFP_PB0_Msk | SYS_GPB_MFP_PB1_Msk); SYS->GPB_MFP |= (SYS_GPB_MFP_PB0_UART0_RXD | SYS_GPB_MFP_PB1_UART0_TXD); /* Set GPA multi-function pins for PWM0 Channel 0 */ SYS->GPA_MFP &= ~(SYS_GPA_MFP_PA12_Msk); SYS->GPA_MFP |= (SYS_GPA_MFP_PA12_PWM0_CH0); SYS->ALT_MFP4 &= ~(SYS_ALT_MFP4_PA12_Msk); }
void initialize() { CLK_EnableModuleClock(UART0_MODULE); CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_HXT, CLK_CLKDIV_UART(1)); }