void __sramfunc sram_i2c_init(void) { unsigned int div, divl, divh; //enable cru_clkgate8 clock data[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_CLKID(8))); #if defined (CONFIG_MACH_RK2928_SDK) || defined( CONFIG_ARCH_RK3026_TB)||defined(CONFIG_ARCH_RK3028A_TB) cru_writel(CLK_GATE_W_MSK(CLK_GATE_PCLK_I2C1)|CLK_UN_GATE(CLK_GATE_PCLK_I2C1), CLK_GATE_CLKID_CONS(CLK_GATE_PCLK_I2C1)); #else cru_writel(CLK_GATE_W_MSK(CLK_GATE_PCLK_I2C0)|CLK_UN_GATE(CLK_GATE_PCLK_I2C0), CLK_GATE_CLKID_CONS(CLK_GATE_PCLK_I2C0)); #endif data[2] = readl_relaxed(RK2928_GRF_BASE + GRF_GPIO_IOMUX); writel_relaxed(data[2]| I2C_GRF_GPIO_IOMUX, RK2928_GRF_BASE + GRF_GPIO_IOMUX); div = 0x1e; divh = divl = 0xf; writel_relaxed(I2C_CLKDIV_VAL(divl, divh), SRAM_I2C_ADDRBASE + I2C_CLKDIV); data[3] = readl_relaxed(SRAM_I2C_ADDRBASE + I2C_CLKDIV); }
void __sramfunc sram_i2c_init() { unsigned int div, divl, divh; //enable cru_clkgate8 clock data[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_CLKID(8))); cru_writel(CLK_GATE_W_MSK(CLK_GATE_PCLK_I2C1)|CLK_UN_GATE(CLK_GATE_PCLK_I2C1), CLK_GATE_CLKID_CONS(CLK_GATE_PCLK_I2C1)); data[2] = readl_relaxed(RK30_GRF_BASE + GRF_GPIO_IOMUX); writel_relaxed(data[2]| I2C_GRF_GPIO_IOMUX, RK30_GRF_BASE + GRF_GPIO_IOMUX); div = 0x1e; divh = divl = 0xf; writel_relaxed(I2C_CLKDIV_VAL(divl, divh), SRAM_I2C_ADDRBASE + I2C_CLKDIV); data[3] = readl_relaxed(SRAM_I2C_ADDRBASE + I2C_CLKDIV); }