void BOARD_BootClockRUN(void)
{
CLOCK_SetSimSafeDivs();
CLOCK_InitOsc0(&g_defaultClockConfigRun.oscConfig);
CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ);
CLOCK_BootToPeeMode(g_defaultClockConfigRun.mcgConfig.oscsel, kMCG_PllClkSelPll0,
&g_defaultClockConfigRun.mcgConfig.pll0Config);
CLOCK_SetInternalRefClkConfig(g_defaultClockConfigRun.mcgConfig.irclkEnableMode,
g_defaultClockConfigRun.mcgConfig.ircs, g_defaultClockConfigRun.mcgConfig.fcrdiv);
CLOCK_SetSimConfig(&g_defaultClockConfigRun.simConfig);
SystemCoreClock = g_defaultClockConfigRun.coreClock;
}
void BOARD_BootClockRUN(void)
{
/* Set the system clock dividers in SIM to safe value. */
CLOCK_SetSimSafeDivs();
/* Configure RTC clock including enabling RTC oscillator. */
CLOCK_CONFIG_SetRtcClock(RTC_OSC_CAP_LOAD_0PF, RTC_RTC32KCLK_PERIPHERALS_ENABLED);
/* Enable IRC48M oscillator for K24 as workaround because there is not enabled the oscillator automatically. */
CLOCK_CONFIG_EnableIrc48MOsc();
/* Configure FLL external reference divider (FRDIV). */
CLOCK_CONFIG_SetFllExtRefDiv(g_defaultClockConfigRun.mcgConfig.frdiv);
/* Set MCG to PEE mode. */
CLOCK_BootToPeeMode(g_defaultClockConfigRun.mcgConfig.oscsel,
kMCG_PllClkSelPll0,
&g_defaultClockConfigRun.mcgConfig.pll0Config);
/* Set the clock configuration in SIM module. */
CLOCK_SetSimConfig(&g_defaultClockConfigRun.simConfig);
/* Set SystemCoreClock variable. */
SystemCoreClock = g_defaultClockConfigRun.coreClock;
/* Set CLKOUT source. */
CLOCK_SetClkOutClock(SIM_CLKOUT_SEL_FLEXBUS_CLK);
}
/**
*
* @brief Initialize the system clock
*
* This routine will configure the multipurpose clock generator (MCG) to
* set up the system clock.
* The MCG has nine possible modes, including Stop mode. This routine assumes
* that the current MCG mode is FLL Engaged Internal (FEI), as from reset.
* It transitions through the FLL Bypassed External (FBE) and
* PLL Bypassed External (PBE) modes to get to the desired
* PLL Engaged External (PEE) mode and generate the maximum 120 MHz system
* clock.
*
* @return N/A
*
*/
static ALWAYS_INLINE void clkInit(void)
{
CLOCK_SetSimSafeDivs();
CLOCK_InitOsc0(&oscConfig);
CLOCK_SetXtal0Freq(CONFIG_OSC_XTAL0_FREQ);
CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &pll0Config);
CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow,
CONFIG_MCG_FCRDIV);
CLOCK_SetSimConfig(&simConfig);
#if CONFIG_ETH_MCUX
CLOCK_SetEnetTime0Clock(TIMESRC_OSCERCLK);
#endif
#if CONFIG_USB_KINETIS
CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcPll0,
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
#endif
}
void BOARD_BootClockHSRUN(void)
{
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
SMC_SetPowerModeHsrun(SMC);
while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
{
}
CLOCK_SetSimSafeDivs();
CLOCK_InitOsc0(&g_defaultClockConfigHsrun.oscConfig);
CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ);
CLOCK_BootToPeeMode(g_defaultClockConfigHsrun.mcgConfig.oscsel, kMCG_PllClkSelPll0,
&g_defaultClockConfigHsrun.mcgConfig.pll0Config);
CLOCK_SetInternalRefClkConfig(g_defaultClockConfigHsrun.mcgConfig.irclkEnableMode,
g_defaultClockConfigHsrun.mcgConfig.ircs, g_defaultClockConfigHsrun.mcgConfig.fcrdiv);
CLOCK_SetSimConfig(&g_defaultClockConfigHsrun.simConfig);
SystemCoreClock = g_defaultClockConfigHsrun.coreClock;
}
void BOARD_BootClockVLPR(void)
{
/*
* Core clock: 4MHz
* Bus clock: 4MHz
*/
const sim_clock_config_t simConfig = {
.pllFllSel = 0U, /* PLLFLLSEL select MCG FLL. */
.er32kSrc = 2U, /* ERCLK32K selection, use RTC. */
.clkdiv1 = 0x00040000U, /* SIM_CLKDIV1. */
};
CLOCK_SetSimSafeDivs();
CLOCK_BootToBlpiMode(0U, kMCG_IrcFast, kMCG_IrclkEnable);
CLOCK_SetSimConfig(&simConfig);
SystemCoreClock = 4000000U;
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
SMC_SetPowerModeVlpr(SMC);
while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
{
}
}
void BOARD_BootClockRUN(void)
{
/*
* Core clock: 72MHz
* Bus clock: 36MHz
* Flash clock: 26MHz
*/
const mcg_pll_config_t pll0Config = {
.enableMode = 0U, .prdiv = 0x07U, .vdiv = 0x0CU,
};
const sim_clock_config_t simConfig = {
.pllFllSel = 1U, /* PLLFLLSEL select MCG PLL. */
.er32kSrc = 3U, /* ERCLK32K selection, use LPO 1 kHz. */
.clkdiv1 = 0x01020000U, /* SIM_CLKDIV1. */
};
CLOCK_SetSimSafeDivs();
BOARD_InitOsc0();
CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &pll0Config);
CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow, 0);
CLOCK_SetSimConfig(&simConfig);
SystemCoreClock = 72000000U;
}
void BOARD_InitOsc0(void)
{
const osc_config_t oscConfig = {.freq = BOARD_XTAL0_CLK_HZ,
.capLoad = 10,
.workMode = kOSC_ModeExt,
.oscerConfig = {
.enableMode = kOSC_ErClkEnable,
#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
.erclkDiv = 0U,
#endif
}};
CLOCK_InitOsc0(&oscConfig);
/* Passing the XTAL0 frequency to clock driver. */
CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ);
/* Use RTC_CLKIN input clock directly. */
CLOCK_SetXtal32Freq(BOARD_XTAL32K_CLK_HZ);
}
void BOARD_BootClockVLPR(void)
{
/*
* Core clock: 4MHz
*/
const sim_clock_config_t simConfig = {
.pllFllSel = 3U, /* PLLFLLSEL select IRC48MCLK. */
.pllFllDiv = 0U, /* PLLFLLSEL clock divider divisor. */
.pllFllFrac = 0U, /* PLLFLLSEL clock divider fraction. */
.er32kSrc = 2U, /* ERCLK32K selection, use RTC. */
.clkdiv1 = 0x03040000U, /* SIM_CLKDIV1. */
};
CLOCK_SetSimSafeDivs();
CLOCK_BootToBlpiMode(0U, kMCG_IrcFast, kMCG_IrclkEnable);
CLOCK_SetSimConfig(&simConfig);
SystemCoreClock = 4000000U;
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
SMC_SetPowerModeVlpr(SMC);
while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
{
}
}
void BOARD_BootClockRUN(void)
{
/*
* Core clock: 72MHz
*/
const mcg_pll_config_t pll0Config = {
.enableMode = 0U, .prdiv = 0x00U, .vdiv = 0x08U,
};
const sim_clock_config_t simConfig = {
.pllFllSel = 1U, /* PLLFLLSEL select PLL. */
.pllFllDiv = 0U, /* PLLFLLSEL clock divider divisor. */
.pllFllFrac = 0U, /* PLLFLLSEL clock divider fraction. */
.er32kSrc = 2U, /* ERCLK32K selection, use RTC. */
.clkdiv1 = 0x15051000U, /* SIM_CLKDIV1. */
};
CLOCK_SetSimSafeDivs();
BOARD_InitOsc0();
CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &pll0Config);
CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow, 0);
CLOCK_SetSimConfig(&simConfig);
SystemCoreClock = 72000000U;
}
void BOARD_BootClockHSRUN(void)
{
/*
* Core clock: 96MHz
*/
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
SMC_SetPowerModeHsrun(SMC);
while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
{
}
CLOCK_SetSimSafeDivs();
BOARD_InitOsc0();
const sim_clock_config_t simConfig = {
.pllFllSel = 1U, /* PLLFLLSEL select PLL. */
.pllFllDiv = 0U, /* PLLFLLSEL clock divider divisor. */
.pllFllFrac = 0U, /* PLLFLLSEL clock divider fraction. */
.er32kSrc = 2U, /* ERCLK32K selection, use RTC. */
.clkdiv1 = 0x03030000U, /* SIM_CLKDIV1. */
};
const mcg_pll_config_t pll0Config = {
.enableMode = 0U, .prdiv = 0x00U, .vdiv = 0x00U,
};
CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &pll0Config);
CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow, 0);
CLOCK_SetSimConfig(&simConfig);
SystemCoreClock = 96000000U;
}
void BOARD_InitOsc0(void)
{
const osc_config_t oscConfig = {.freq = BOARD_XTAL0_CLK_HZ,
.capLoad = 0,
.workMode = kOSC_ModeOscLowPower,
.oscerConfig = {
.enableMode = kOSC_ErClkEnable,
#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
.erclkDiv = 0U,
#endif
}};
CLOCK_InitOsc0(&oscConfig);
/* Passing the XTAL0 frequency to clock driver. */
CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ);
CLOCK_SetXtal32Freq(BOARD_XTAL32K_CLK_HZ);
}
void APP_BootToPeeExample(void)
{
CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &g_pllConfig);
assert(kMCG_ModePEE == CLOCK_GetMode());
}
static ALWAYS_INLINE void clkInit(void)
{
/*
* Core clock: 48MHz
* Bus clock: 24MHz
*/
const mcg_pll_config_t pll0Config = {
.enableMode = 0U, .prdiv = CONFIG_MCG_PRDIV0, .vdiv = CONFIG_MCG_VDIV0,
};
const sim_clock_config_t simConfig = {
.pllFllSel = 1U, /* PLLFLLSEL select PLL. */
.er32kSrc = 3U, /* ERCLK32K selection, use LPO. */
.clkdiv1 = 0x10010000U, /* SIM_CLKDIV1. */
};
const osc_config_t oscConfig = {.freq = CONFIG_OSC_XTAL0_FREQ,
.capLoad = 0,
#if defined(CONFIG_OSC_EXTERNAL)
.workMode = kOSC_ModeExt,
#elif defined(CONFIG_OSC_LOW_POWER)
.workMode = kOSC_ModeOscLowPower,
#elif defined(CONFIG_OSC_HIGH_GAIN)
.workMode = kOSC_ModeOscHighGain,
#else
#error "An oscillator mode must be defined"
#endif
.oscerConfig = {
.enableMode = kOSC_ErClkEnable,
#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && \
FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
.erclkDiv = 0U,
#endif
} };
CLOCK_SetSimSafeDivs();
CLOCK_InitOsc0(&oscConfig);
/* Passing the XTAL0 frequency to clock driver. */
CLOCK_SetXtal0Freq(CONFIG_OSC_XTAL0_FREQ);
CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &pll0Config);
CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow, 0);
CLOCK_SetSimConfig(&simConfig);
#ifdef CONFIG_UART_MCUX_LPSCI_0
CLOCK_SetLpsci0Clock(LPSCI0SRC_MCGFLLCLK);
#endif
}
static int kl2x_init(struct device *arg)
{
ARG_UNUSED(arg);
int oldLevel; /* old interrupt lock level */
/* disable interrupts */
oldLevel = irq_lock();
/* Disable the watchdog */
SIM->COPC = 0;
/* Initialize system clock to 48 MHz */
clkInit();
/*
* install default handler that simply resets the CPU
* if configured in the kernel, NOP otherwise
*/
NMI_INIT();
/* restore interrupt state */
irq_unlock(oldLevel);
return 0;
}
SYS_INIT(kl2x_init, PRE_KERNEL_1, 0);
void BOARD_BootClockVLPR(void)
{
/*
* Core clock: 4MHz
*/
const sim_clock_config_t simConfig = {
.pllFllSel = 0U, /* PLLFLLSEL select FLL. */
.er32kSrc = 2U, /* ERCLK32K selection, use RTC. */
.clkdiv1 = 0x00030000U, /* SIM_CLKDIV1. */
};
CLOCK_SetSimSafeDivs();
CLOCK_BootToBlpiMode(0U, kMCG_IrcFast, kMCG_IrclkEnable);
CLOCK_SetSimConfig(&simConfig);
SystemCoreClock = 4000000U;
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
SMC_SetPowerModeVlpr(SMC, false);
while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
{
}
}
void BOARD_BootClockRUN(void)
{
/*
* Core clock: 48MHz
* Bus clock: 24MHz
*/
const mcg_pll_config_t pll0Config = {
.enableMode = 0U,
.prdiv = 0x1U,
.vdiv = 0x0U,
};
const sim_clock_config_t simConfig = {
.pllFllSel = 1U, /* PLLFLLSEL select PLL. */
.er32kSrc = 2U, /* ERCLK32K selection, use RTC. */
.clkdiv1 = 0x00010000U, /* SIM_CLKDIV1. */
};
/* Perform initialization of the wireless modem clock output */
if (BOARD_ExtClk_Setup_HookUp(BOARD_XTAL0_CLK_HZ) != 1U)
{
/* If the initialization was not successfully, do not continue with clock setup */
return;
}
CLOCK_SetSimSafeDivs();
BOARD_InitOsc0();
CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &pll0Config);
CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow, 0);
CLOCK_SetSimConfig(&simConfig);
SystemCoreClock = 48000000U;
}
void BOARD_InitOsc0(void)
{
const osc_config_t oscConfig = {.freq = BOARD_XTAL0_CLK_HZ,
.capLoad = 0,
.workMode = kOSC_ModeOscLowPower,
.oscerConfig = {
.enableMode = kOSC_ErClkEnable | kOSC_ErClkEnableInStop,
#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
.erclkDiv = 0U,
#endif
}};
CLOCK_InitOsc0(&oscConfig);
/* Passing the XTAL0 frequency to clock driver. */
CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ);
}
