static uint32_t CLOCK_GetPeriphClkFreq(void) { uint32_t freq; /* Periph_clk2_clk ---> Periph_clk */ if (CCM->CBCDR & CCM_CBCDR_PERIPH_CLK_SEL_MASK) { switch (CCM->CBCMR & CCM_CBCMR_PERIPH_CLK2_SEL_MASK) { /* Pll3_sw_clk ---> Periph_clk2_clk ---> Periph_clk */ case CCM_CBCMR_PERIPH_CLK2_SEL(0U): freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1); break; /* Osc_clk ---> Periph_clk2_clk ---> Periph_clk */ case CCM_CBCMR_PERIPH_CLK2_SEL(1U): freq = CLOCK_GetOscFreq(); break; case CCM_CBCMR_PERIPH_CLK2_SEL(2U): freq = CLOCK_GetPllFreq(kCLOCK_PllSys); break; case CCM_CBCMR_PERIPH_CLK2_SEL(3U): default: freq = 0U; break; } freq /= (((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >> CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) + 1U); } /* Pre_Periph_clk ---> Periph_clk */ else { switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
uint32_t serial_get_clock(void) { uint32_t clock_freq; /* We assume default PLL and divider settings, and the only variable * from application is use PLL3 source or OSC source */ if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */ { clock_freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U); } else { clock_freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U); } return clock_freq; }
/* Get debug console frequency. */ uint32_t GetUartSrcFreq(void) { uint32_t freq; /* To make it simple, we assume default PLL and divider settings, and the only variable from application is use PLL3 source or OSC source */ if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */ { freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U); } else { freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U); } return freq; }