/*******************************************************************************
* Code
******************************************************************************/
void initialize_enet_hardware(void)
{
port_pin_config_t configENET = {0};
/* Disable MPU. */
MPU->CESR &= ~MPU_CESR_VLD_MASK;
CLOCK_EnableClock(kCLOCK_PortC);
CLOCK_EnableClock(kCLOCK_PortB);
/* Affects PORTC_PCR16 register */
PORT_SetPinMux(PORTC, 16u, kPORT_MuxAlt4);
/* Affects PORTC_PCR17 register */
PORT_SetPinMux(PORTC, 17u, kPORT_MuxAlt4);
/* Affects PORTC_PCR18 register */
PORT_SetPinMux(PORTC, 18u, kPORT_MuxAlt4);
/* Affects PORTC_PCR19 register */
PORT_SetPinMux(PORTC, 19u, kPORT_MuxAlt4);
/* Affects PORTB_PCR1 register */
PORT_SetPinMux(PORTB, 1u, kPORT_MuxAlt4);
configENET.openDrainEnable = kPORT_OpenDrainEnable;
configENET.mux = kPORT_MuxAlt4;
configENET.pullSelect = kPORT_PullUp;
/* Ungate the port clock */
CLOCK_EnableClock(kCLOCK_PortA);
/* Affects PORTB_PCR0 register */
PORT_SetPinConfig(PORTB, 0u, &configENET);
/* Affects PORTA_PCR13 register */
PORT_SetPinMux(PORTA, 13u, kPORT_MuxAlt4);
/* Affects PORTA_PCR12 register */
PORT_SetPinMux(PORTA, 12u, kPORT_MuxAlt4);
/* Affects PORTA_PCR14 register */
PORT_SetPinMux(PORTA, 14u, kPORT_MuxAlt4);
/* Affects PORTA_PCR5 register */
PORT_SetPinMux(PORTA, 5u, kPORT_MuxAlt4);
/* Affects PORTA_PCR16 register */
PORT_SetPinMux(PORTA, 16u, kPORT_MuxAlt4);
/* Affects PORTA_PCR17 register */
PORT_SetPinMux(PORTA, 17u, kPORT_MuxAlt4);
/* Affects PORTA_PCR15 register */
PORT_SetPinMux(PORTA, 15u, kPORT_MuxAlt4);
/* Affects PORTA_PCR28 register */
PORT_SetPinMux(PORTA, 28u, kPORT_MuxAlt4);
/* Select the Ethernet timestamp clock source */
CLOCK_SetEnetTime0Clock(0x2);
}
/**
*
* @brief Initialize the system clock
*
* This routine will configure the multipurpose clock generator (MCG) to
* set up the system clock.
* The MCG has nine possible modes, including Stop mode. This routine assumes
* that the current MCG mode is FLL Engaged Internal (FEI), as from reset.
* It transitions through the FLL Bypassed External (FBE) and
* PLL Bypassed External (PBE) modes to get to the desired
* PLL Engaged External (PEE) mode and generate the maximum 120 MHz system
* clock.
*
* @return N/A
*
*/
static ALWAYS_INLINE void clkInit(void)
{
CLOCK_SetSimSafeDivs();
CLOCK_InitOsc0(&oscConfig);
CLOCK_SetXtal0Freq(CONFIG_OSC_XTAL0_FREQ);
CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &pll0Config);
CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow,
CONFIG_MCG_FCRDIV);
CLOCK_SetSimConfig(&simConfig);
#if CONFIG_ETH_MCUX
CLOCK_SetEnetTime0Clock(TIMESRC_OSCERCLK);
#endif
#if CONFIG_USB_KINETIS
CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcPll0,
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
#endif
}