t_stat tto_wr (int32 data, int32 PA, int32 access)
{
switch ((PA >> 1) & 01) { /* decode PA<1> */
case 00: /* tto csr */
if (PA & 1)
return SCPE_OK;
if ((data & CSR_IE) == 0)
CLR_INT (TTO);
else if ((tto_csr & (CSR_DONE + CSR_IE)) == CSR_DONE)
SET_INT (TTO);
tto_csr = (tto_csr & ~TTOCSR_RW) | (data & TTOCSR_RW);
return SCPE_OK;
case 01: /* tto buf */
if ((PA & 1) == 0)
tto_unit.buf = data & 0377;
tto_csr = tto_csr & ~CSR_DONE;
CLR_INT (TTO);
sim_activate (&tto_unit, tto_unit.wait);
return SCPE_OK;
} /* end switch PA */
return SCPE_NXM;
}
t_stat ptp_wr (int32 data, int32 PA, int32 access)
{
switch ((PA >> 1) & 01) { /* decode PA<1> */
case 0: /* ptp csr */
if (PA & 1)
return SCPE_OK;
if ((data & CSR_IE) == 0)
CLR_INT (PTP);
else if (((ptp_csr & CSR_IE) == 0) && (ptp_csr & (CSR_ERR | CSR_DONE)))
SET_INT (PTP);
ptp_csr = (ptp_csr & ~PTPCSR_RW) | (data & PTPCSR_RW);
return SCPE_OK;
case 1: /* ptp buf */
if ((PA & 1) == 0)
ptp_unit.buf = data & 0377;
ptp_csr = ptp_csr & ~CSR_DONE;
CLR_INT (PTP);
if (ptp_unit.flags & UNIT_ATT) /* file to write? */
sim_activate (&ptp_unit, ptp_unit.wait);
else sim_activate (&ptp_unit, 0); /* error if not */
return SCPE_OK;
} /* end switch PA */
return SCPE_NXM; /* can't get here */
}
t_stat ptr_wr (int32 data, int32 PA, int32 access)
{
switch ((PA >> 1) & 01) { /* decode PA<1> */
case 0: /* ptr csr */
if (PA & 1)
return SCPE_OK;
if ((data & CSR_IE) == 0)
CLR_INT (PTR);
else if (((ptr_csr & CSR_IE) == 0) && (ptr_csr & (CSR_ERR | CSR_DONE)))
SET_INT (PTR);
if (data & CSR_GO) {
ptr_csr = (ptr_csr & ~CSR_DONE) | CSR_BUSY;
CLR_INT (PTR);
if (ptr_unit.flags & UNIT_ATT) /* data to read? */
sim_activate (&ptr_unit, ptr_unit.wait);
else sim_activate (&ptr_unit, 0); /* error if not */
}
ptr_csr = (ptr_csr & ~PTRCSR_RW) | (data & PTRCSR_RW);
return SCPE_OK;
case 1: /* ptr buf */
return SCPE_OK;
} /* end switch PA */
return SCPE_NXM; /* can't get here */
}
t_stat
vt_reset(DEVICE *dptr)
{
if (!(dptr->flags & DEV_DIS))
vt11_reset();
CLR_INT (VTST);
CLR_INT (VTLP);
CLR_INT (VTCH);
CLR_INT (VTNM);
sim_cancel (&vt_unit); /* deactivate unit */
return auto_config ("VT", (dptr->flags & DEV_DIS) ? 0 : 1);
}
void iccs_wr (int32 data)
{
if ((data & CSR_IE) == 0)
CLR_INT (CLK);
clk_csr = (clk_csr & ~CLKCSR_RW) | (data & CLKCSR_RW);
return;
}
t_stat ttp_reset (DEVICE *dptr)
{
if (dptr->flags & DEV_DIS)
sim_cancel (&ttp_unit[TTI]);
else sim_activate_abs (&ttp_unit[TTI], KBD_WAIT (ttp_unit[TTI].wait, lfc_poll));
sim_cancel (&ttp_unit[TTO]);
CLR_INT (v_TTP); /* clear int */
CLR_ENB (v_TTP);
CLR_INT (v_TTP + 1); /* disable int */
CLR_ENB (v_TTP + 1);
ttp_karm = ttp_tarm = 0; /* disarm int */
ttp_cmd = 0;
ttp_sta = 0;
ttp_kchp = 0;
return SCPE_OK;
}
int32 ptrio (int32 inst, int32 fnc, int32 dat, int32 dev)
{
switch (inst) { /* case on opcode */
case ioOCP: /* OCP */
if (fnc & 016) /* only fnc 0,1 */
return IOBADFNC (dat);
ptr_motion = fnc ^ 1;
if (fnc) /* fnc 1? stop */
sim_cancel (&ptr_unit);
else sim_activate (&ptr_unit, ptr_unit.wait); /* fnc 0? start */
break;
case ioSKS: /* SKS */
if (fnc & 013) /* only fnc 0,4 */
return IOBADFNC (dat);
if (((fnc == 000) && TST_INT (INT_PTR)) || /* fnc 0? skip rdy */
((fnc == 004) && !TST_INTREQ (INT_PTR))) /* fnc 4? skip !int */
return IOSKIP (dat);
break;
case ioINA: /* INA */
if (fnc) /* only fnc 0 */
return IOBADFNC (dat);
if (TST_INT (INT_PTR)) { /* ready? */
CLR_INT (INT_PTR); /* clear ready */
if (ptr_motion) /* if motion, restart */
sim_activate (&ptr_unit, ptr_unit.wait);
return IOSKIP (ptr_unit.buf | dat); /* ret buf, skip */
}
break;
} /* end case op */
return dat;
}
void rp_updsta (int32 newa, int32 newb)
{
int32 f;
UNIT *uptr;
uptr = rp_dev.units + GET_UNIT (rp_sta);
rp_sta = (rp_sta & ~(STA_DYN | STA_ERR)) | newa;
rp_stb = (rp_stb & ~STB_DYN) | newb;
if (uptr->flags & UNIT_WPRT)
rp_sta = rp_sta | STA_SUWP;
if ((uptr->flags & UNIT_ATT) == 0)
rp_stb = rp_stb | STB_SUFU | STB_SUNR;
else if (sim_is_active (uptr)) {
f = (uptr->FUNC) & STA_M_FUNC;
if ((f == FN_SEEK) || (f == FN_RECAL))
rp_stb = rp_stb | STB_SUSU | STB_SUNR;
}
else if (uptr->CYL >= RP_NUMCY)
rp_sta = rp_sta | STA_SUSI;
if ((rp_sta & STA_EFLGS) || (rp_stb & STB_EFLGS))
rp_sta = rp_sta | STA_ERR;
if (((rp_sta & (STA_ERR | STA_DON)) && (rp_sta & STA_IED)) ||
((rp_stb & STB_ATTN) && (rp_sta & STA_IEA)))
SET_INT (RP);
else CLR_INT (RP);
return;
}
t_stat dp_reset (DEVICE *dptr)
{
int32 i;
dp_fnc = 0;
dp_cw1 = 0;
dp_cw2 = 0;
dp_sta = 0;
dp_buf = 0;
dp_xip = 0;
dp_eor = 0;
dp_dma = 0;
dp_csum = 0;
dp_rptr = 0;
dp_wptr = 0;
dp_bctr = 0;
dp_gap = 0;
dp_defint = 0;
for (i = 0; i < DP_NUMDRV; i++) { /* loop thru drives */
sim_cancel (&dp_unit[i]); /* cancel activity */
dp_unit[i].FNC = 0; /* clear function */
dp_unit[i].CYL = 0;
}
CLR_INT (INT_DP); /* clear int, enb */
CLR_ENB (INT_DP);
return SCPE_OK;
}
void txdb_wr (int32 data)
{
tto_unit.buf = data & 0377;
tto_csr = tto_csr & ~CSR_DONE;
CLR_INT (TTO);
sim_activate (&tto_unit, tto_unit.wait);
return;
}
t_stat tti_reset (DEVICE *dptr)
{
tti_unit.buf = 0;
tti_csr = 0;
CLR_INT (TTI);
sim_activate_abs (&tti_unit, KBD_WAIT (tti_unit.wait, tmr_poll));
return SCPE_OK;
}
t_stat tto_reset (DEVICE *dptr)
{
tto_unit.buf = 0;
tto_csr = CSR_DONE;
CLR_INT (TTO);
sim_cancel (&tto_unit); /* deactivate unit */
return SCPE_OK;
}
t_stat pclk_reset (DEVICE *dptr)
{
pclk_csr = 0; /* clear reg */
pclk_csb = 0;
pclk_ctr = 0;
CLR_INT (PCLK); /* clear int */
sim_cancel (&pclk_unit); /* cancel */
return auto_config (0, 0);
}
t_stat tti_reset (DEVICE *dptr)
{
tmxr_set_console_units (&tti_unit, &tto_unit);
tti_unit.buf = 0;
tti_csr = 0;
CLR_INT (TTI);
sim_activate (&tti_unit, KBD_WAIT (tti_unit.wait, tmr_poll));
return SCPE_OK;
}
int32 rxdb_rd (void)
{
int32 t = tti_unit.buf; /* char + error */
tti_csr = tti_csr & ~CSR_DONE; /* clr done */
tti_unit.buf = tti_unit.buf & 0377; /* clr errors */
CLR_INT (TTI);
return t;
}
void iccs_wr (int32 data)
{
if ((data & CSR_IE) == 0)
CLR_INT (CLK);
if (data & CSR_DONE) /* Interrupt Acked? */
sim_rtcn_tick_ack (20, TMR_CLK); /* Let timers know */
clk_csr = (clk_csr & ~CLKCSR_RW) | (data & CLKCSR_RW);
return;
}
void txcs_wr (int32 data)
{
if ((data & CSR_IE) == 0)
CLR_INT (TTO);
else if ((tto_csr & (CSR_DONE + CSR_IE)) == CSR_DONE)
SET_INT (TTO);
tto_csr = (tto_csr & ~TTOCSR_RW) | (data & TTOCSR_RW);
return;
}
t_stat ptr_reset (DEVICE *dptr)
{
ptr_unit.buf = 0;
ptr_csr = 0;
if ((ptr_unit.flags & UNIT_ATT) == 0)
ptr_csr = ptr_csr | CSR_ERR;
CLR_INT (PTR);
sim_cancel (&ptr_unit);
return SCPE_OK;
}
t_stat ptp_reset (DEVICE *dptr)
{
ptp_unit.buf = 0;
ptp_csr = CSR_DONE;
if ((ptp_unit.flags & UNIT_ATT) == 0)
ptp_csr = ptp_csr | CSR_ERR;
CLR_INT (PTP);
sim_cancel (&ptp_unit); /* deactivate unit */
return SCPE_OK;
}
t_stat pclk_reset (DEVICE *dptr)
{
pclk_csr = 0; /* clear reg */
pclk_csb = 0;
pclk_ctr = 0;
CLR_INT (PCLK); /* clear int */
sim_cancel (&pclk_unit); /* cancel */
pclk_unit.wait = xtim[0]; /* reset delay */
return SCPE_OK;
}
t_stat ptp_reset (DEVICE *dptr)
{
CLR_INT (INT_PTP); /* clear ready, enb */
CLR_ENB (INT_PTP);
ptp_power = 0; /* power off */
ptp_unit.buf = 0; /* clear buffer */
ptp_unit.STA = 0;
sim_cancel (&ptp_unit); /* deactivate unit */
return SCPE_OK;
}
t_stat ptr_reset (DEVICE *dptr)
{
CLR_INT (INT_PTR); /* clear ready, enb */
CLR_ENB (INT_PTR);
ptr_unit.buf = 0; /* clear buffer */
ptr_unit.STA = 0;
ptr_motion = 0; /* unit stopped */
sim_cancel (&ptr_unit); /* deactivate unit */
return SCPE_OK;
}
t_stat ptr_reset (DEVICE *dptr)
{
ptr_unit.buf = 0;
ptr_csr = 0;
if ((ptr_unit.flags & UNIT_ATT) == 0)
ptr_csr = ptr_csr | CSR_ERR;
CLR_INT (PTR);
sim_cancel (&ptr_unit);
return auto_config (dptr->name, 1);
}
t_stat
lpt_reset(DEVICE * dptr)
{
lpt_unit.buf = 0;
lpt_csr = CSR_DONE;
if ((lpt_unit.flags & UNIT_ATT) == 0)
lpt_csr = lpt_csr | CSR_ERR;
CLR_INT(LPT);
sim_cancel(&lpt_unit); /* deactivate unit */
return SCPE_OK;
}
void ttox_clr_done (int32 ln)
{
ttox_done = ttox_done & ~(1 << ln);
if (ttox_done) {
SET_INT (TTO1);
}
else {
CLR_INT (TTO1);
}
return;
}
t_stat clk_wr (int32 data, int32 PA, int32 access)
{
if (clk_fnxm) return SCPE_NXM; /* not there??? */
if (PA & 1) return SCPE_OK;
clk_csr = (clk_csr & ~CLKCSR_RW) | (data & CLKCSR_RW);
if (CPUT (HAS_LTCM) && ((data & CSR_DONE) == 0)) /* monitor bit? */
clk_csr = clk_csr & ~CSR_DONE; /* clr if zero */
if ((((clk_csr & CSR_IE) == 0) && !clk_fie) || /* unless IE+DONE */
((clk_csr & CSR_DONE) == 0)) CLR_INT (CLK); /* clr intr */
return SCPE_OK;
}
void txdb_wr (int32 data)
{
if (data & TXDB_SEL) { /* internal function? */
txdb_func (data);
return;
}
tto_unit.buf = data & 0377;
tto_csr = tto_csr & ~CSR_DONE;
CLR_INT (TTO);
sim_activate (&tto_unit, tto_unit.wait);
return;
}
int32 rxdb_rd (void)
{
int32 t = tti_unit.buf; /* char + error */
if (tti_csr & CSR_DONE) { /* Input pending ? */
tti_csr = tti_csr & ~CSR_DONE; /* clr done */
tti_unit.buf = tti_unit.buf & 0377; /* clr errors */
CLR_INT (TTI);
sim_activate_after_abs (&tti_unit, tti_unit.wait); /* check soon for more input */
}
return t;
}
int32 ptpio (int32 inst, int32 fnc, int32 dat, int32 dev)
{
switch (inst) { /* case on opcode */
case ioOCP: /* OCP */
if (fnc & 016) /* only fnc 0,1 */
return IOBADFNC (dat);
if (fnc) { /* fnc 1? pwr off */
CLR_INT (INT_PTP); /* not ready */
ptp_power = 0; /* turn off power */
sim_cancel (&ptp_unit); /* stop punch */
}
else if (ptp_power == 0) /* fnc 0? start */
sim_activate (&ptp_unit, ptp_ptime);
break;
case ioSKS: /* SKS */
if ((fnc & 012) || (fnc == 005)) /* only 0, 1, 4 */
return IOBADFNC (dat);
if (((fnc == 000) && TST_INT (INT_PTP)) || /* fnc 0? skip rdy */
((fnc == 001) && /* fnc 1? skip ptp on */
(ptp_power || sim_is_active (&ptp_unit))) ||
((fnc == 004) && !TST_INTREQ (INT_PTP))) /* fnc 4? skip !int */
return IOSKIP (dat);
break;
case ioOTA: /* OTA */
if (fnc) /* only fnc 0 */
return IOBADFNC (dat);
if (TST_INT (INT_PTP)) { /* if ptp ready */
CLR_INT (INT_PTP); /* clear ready */
ptp_unit.buf = dat & 0377; /* store byte */
sim_activate (&ptp_unit, ptp_unit.wait);
return IOSKIP (dat); /* skip return */
}
break;
}
return dat;
}
t_stat pclk_wr (int32 data, int32 PA, int32 access)
{
int32 old_csr = pclk_csr;
int32 rv;
switch ((PA >> 1) & 03) {
case 00: /* CSR */
pclk_csr = data & PCLKCSR_WRMASK; /* clear and write */
CLR_INT (PCLK); /* clr intr */
rv = CSR_GETRATE (pclk_csr); /* new rate */
if ((pclk_csr & CSR_GO) == 0) { /* stopped? */
pclk_ctr = pclk_get_ctr (); /* save current value */
sim_cancel (&pclk_unit); /* cancel */
if (data & CSR_FIX) { /* fix? tick */
pclk_ctr = DMASK & (pclk_ctr + (pclk_csr & CSR_UPDN)? 1 : -1);
if (pclk_ctr == 0)
pclk_svc (&pclk_unit);
}
}
else if (((old_csr & CSR_GO) == 0) || /* run 0 -> 1? */
(rv != CSR_GETRATE (old_csr))) { /* rate change? */
sim_cancel (&pclk_unit); /* cancel */
pclk_set_ctr (pclk_csb); /* start clock */
}
break;
case 01: /* buffer */
pclk_csb = data; /* store ctr */
pclk_set_ctr (data);
pclk_csr = pclk_csr & ~(CSR_ERR | CSR_DONE); /* clr err, done */
CLR_INT (PCLK); /* clr intr */
break;
case 02: /* counter */
break; /* read only */
}
return SCPE_OK;
}
