static void cn23xx_vf_setup_global_output_regs(struct octeon_device *oct) { u32 reg_val; u32 q_no; for (q_no = 0; q_no < (oct->sriov_info.rings_per_vf); q_no++) { octeon_write_csr(oct, CN23XX_VF_SLI_OQ_PKTS_CREDIT(q_no), 0xFFFFFFFF); reg_val = octeon_read_csr(oct, CN23XX_VF_SLI_OQ_PKTS_SENT(q_no)); reg_val &= 0xEFFFFFFFFFFFFFFFL; reg_val = octeon_read_csr(oct, CN23XX_VF_SLI_OQ_PKT_CONTROL(q_no)); /* clear IPTR */ reg_val &= ~CN23XX_PKT_OUTPUT_CTL_IPTR; /* set DPTR */ reg_val |= CN23XX_PKT_OUTPUT_CTL_DPTR; /* reset BMODE */ reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_BMODE); /* No Relaxed Ordering, No Snoop, 64-bit Byte swap * for Output Queue ScatterList reset ROR_P, NSR_P */ reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ROR_P); reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_NSR_P); #ifdef __LITTLE_ENDIAN_BITFIELD reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ES_P); #else reg_val |= (CN23XX_PKT_OUTPUT_CTL_ES_P); #endif /* No Relaxed Ordering, No Snoop, 64-bit Byte swap * for Output Queue Data reset ROR, NSR */ reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ROR); reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_NSR); /* set the ES bit */ reg_val |= (CN23XX_PKT_OUTPUT_CTL_ES); /* write all the selected settings */ octeon_write_csr(oct, CN23XX_VF_SLI_OQ_PKT_CONTROL(q_no), reg_val); } }
static void cn23xx_setup_vf_oq_regs(struct octeon_device *oct, u32 oq_no) { struct octeon_droq *droq = oct->droq[oq_no]; octeon_write_csr64(oct, CN23XX_VF_SLI_OQ_BASE_ADDR64(oq_no), droq->desc_ring_dma); octeon_write_csr(oct, CN23XX_VF_SLI_OQ_SIZE(oq_no), droq->max_count); octeon_write_csr(oct, CN23XX_VF_SLI_OQ_BUFF_INFO_SIZE(oq_no), (droq->buffer_size | (OCT_RH_SIZE << 16))); /* Get the mapped address of the pkt_sent and pkts_credit regs */ droq->pkts_sent_reg = (u8 *)oct->mmio[0].hw_addr + CN23XX_VF_SLI_OQ_PKTS_SENT(oq_no); droq->pkts_credit_reg = (u8 *)oct->mmio[0].hw_addr + CN23XX_VF_SLI_OQ_PKTS_CREDIT(oq_no); }