INT32 _stp_trigger_firmware_assert_via_emi(VOID)
{
INT32 status = -1;
INT32 j = 0;
CONSYS_REG_WRITE(CONSYS_AP2CONN_OSC_EN_REG,CONSYS_REG_READ(CONSYS_AP2CONN_OSC_EN_REG) & ~CONSYS_AP2CONN_WAKEUP_BIT);
STP_BTM_INFO_FUNC("enable:dump CONSYS_AP2CONN_OSC_EN_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_AP2CONN_OSC_EN_REG));
usleep_range(64, 96);
CONSYS_REG_WRITE(CONSYS_AP2CONN_OSC_EN_REG,CONSYS_REG_READ(CONSYS_AP2CONN_OSC_EN_REG) | CONSYS_AP2CONN_WAKEUP_BIT);
STP_BTM_INFO_FUNC("disable:dump CONSYS_AP2CONN_OSC_EN_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_AP2CONN_OSC_EN_REG));
do {
if(0 != mtk_wcn_stp_coredump_start_get()){
status = 0;
break;
}
stp_dbg_poll_cpupcr(5 , 1 , 1);
j++;
STP_BTM_INFO_FUNC("Wait for assert message (%d)\n", j);
osal_msleep(20);
if(j > 8)
break;
} while(1);
return status;
}
UINT32 wmt_plat_force_trigger_assert(ENUM_FORCE_TRG_ASSERT_T type)
{
UINT8 * p_virtual_addr = NULL;
switch(type){
case STP_FORCE_TRG_ASSERT_EMI:
WMT_PLAT_INFO_FUNC("[Force Assert] stp_trigger_firmware_assert_via_emi -->\n");
p_virtual_addr = wmt_plat_get_emi_virt_add(EXP_APMEM_CTRL_HOST_OUTBAND_ASSERT_W1);
if(!p_virtual_addr)
{
WMT_PLAT_ERR_FUNC("get virtual address fail\n");
return -1;
}
CONSYS_REG_WRITE(p_virtual_addr, EXP_APMEM_HOST_OUTBAND_ASSERT_MAGIC_W1);
WMT_PLAT_INFO_FUNC("[Force Assert] stp_trigger_firmware_assert_via_emi <--\n");
break;
case STP_FORCE_TRG_ASSERT_DEBUG_PIN:
CONSYS_REG_WRITE(CONSYS_AP2CONN_OSC_EN_REG,CONSYS_REG_READ(CONSYS_AP2CONN_OSC_EN_REG) & ~CONSYS_AP2CONN_WAKEUP_BIT);
WMT_PLAT_INFO_FUNC("enable:dump CONSYS_AP2CONN_OSC_EN_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_AP2CONN_OSC_EN_REG));
usleep_range(64, 96);
CONSYS_REG_WRITE(CONSYS_AP2CONN_OSC_EN_REG,CONSYS_REG_READ(CONSYS_AP2CONN_OSC_EN_REG) | CONSYS_AP2CONN_WAKEUP_BIT);
WMT_PLAT_INFO_FUNC("disable:dump CONSYS_AP2CONN_OSC_EN_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_AP2CONN_OSC_EN_REG));
break;
default:
WMT_PLAT_ERR_FUNC("unknow force trigger assert type\n");
break;
}
return 0;
}
UINT32 mtk_wcn_consys_hw_osc_en_ctrl(UINT32 en)
{
if(en)
{
WMT_PLAT_INFO_FUNC("enable consys sleep mode(turn off 26M)\n");
CONSYS_REG_WRITE(CONSYS_AP2CONN_OSC_EN_REG, CONSYS_REG_READ(CONSYS_AP2CONN_OSC_EN_REG) & ~CONSYS_AP2CONN_OSC_EN_BIT);
}else
{
WMT_PLAT_INFO_FUNC("disable consys sleep mode\n");
CONSYS_REG_WRITE(CONSYS_AP2CONN_OSC_EN_REG, CONSYS_REG_READ(CONSYS_AP2CONN_OSC_EN_REG) | CONSYS_AP2CONN_OSC_EN_BIT);
}
WMT_PLAT_INFO_FUNC("dump CONSYS_AP2CONN_OSC_EN_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_AP2CONN_OSC_EN_REG));
return 0;
}
INT32 mtk_wcn_consys_hw_restore(struct device *device)
{
UINT32 addrPhy = 0;
if (gConEmiPhyBase) {
#if CONSYS_EMI_MPU_SETTING
/*set MPU for EMI share Memory */
WMT_PLAT_INFO_FUNC("setting MPU for EMI share memory\n");
#if defined(CONFIG_ARCH_MT6735)
emi_mpu_set_region_protection(gConEmiPhyBase + SZ_1M / 2,
gConEmiPhyBase + SZ_1M - 1,
13,
SET_ACCESS_PERMISSON(FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
FORBIDDEN, NO_PROTECTION, FORBIDDEN, NO_PROTECTION));
#elif defined(CONFIG_ARCH_MT6735M)
emi_mpu_set_region_protection(gConEmiPhyBase,
gConEmiPhyBase + SZ_1M - 1,
6,
SET_ACCESS_PERMISSON(FORBIDDEN, NO_PROTECTION, FORBIDDEN,
NO_PROTECTION));
#elif defined(CONFIG_ARCH_MT6753)
emi_mpu_set_region_protection(gConEmiPhyBase + SZ_1M / 2,
gConEmiPhyBase + SZ_1M - 1,
13,
SET_ACCESS_PERMISSON(FORBIDDEN, FORBIDDEN, FORBIDDEN,
FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN, NO_PROTECTION));
#else
WMT_PLAT_WARN_FUNC("not define platform config\n");
#endif
#endif
/*consys to ap emi remapping register:10000320, cal remapping address */
addrPhy = (gConEmiPhyBase & 0xFFF00000) >> 20;
/*enable consys to ap emi remapping bit12 */
addrPhy = addrPhy | 0x1000;
CONSYS_REG_WRITE(conn_reg.topckgen_base + CONSYS_EMI_MAPPING_OFFSET,
CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_EMI_MAPPING_OFFSET) | addrPhy);
WMT_PLAT_INFO_FUNC("CONSYS_EMI_MAPPING dump in restore cb(0x%08x)\n",
CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_EMI_MAPPING_OFFSET));
#if 1
pEmibaseaddr = ioremap_nocache(gConEmiPhyBase + SZ_1M / 2, CONSYS_EMI_MEM_SIZE);
#else
pEmibaseaddr = ioremap_nocache(CONSYS_EMI_AP_PHY_BASE, CONSYS_EMI_MEM_SIZE);
#endif
if (pEmibaseaddr) {
WMT_PLAT_WARN_FUNC("EMI mapping OK(0x%p)\n", pEmibaseaddr);
memset_io(pEmibaseaddr, 0, CONSYS_EMI_MEM_SIZE);
} else {
WMT_PLAT_ERR_FUNC("EMI mapping fail\n");
}
} else {
INT32 _stp_trigger_firmware_assert_via_emi(VOID)
{
PUINT8 p_virtual_addr = NULL;
INT32 status = -1;
INT32 i = 0, j = 0;
do {
STP_BTM_INFO_FUNC("[Force Assert] stp_trigger_firmware_assert_via_emi -->\n");
p_virtual_addr = wmt_plat_get_emi_virt_add(EXP_APMEM_CTRL_HOST_OUTBAND_ASSERT_W1);
if(!p_virtual_addr)
{
STP_BTM_ERR_FUNC("get virtual address fail\n");
return -1;
}
CONSYS_REG_WRITE(p_virtual_addr, EXP_APMEM_HOST_OUTBAND_ASSERT_MAGIC_W1);
STP_BTM_INFO_FUNC("[Force Assert] stp_trigger_firmware_assert_via_emi <--\n");
#if 1
//wait for firmware assert
osal_sleep_ms(50);
//if firmware is not assert self, host driver helps it.
do
{
if(0 != mtk_wcn_stp_coredump_start_get()){
status = 0;
break;
}
mtk_wcn_stp_wakeup_consys();
STP_BTM_INFO_FUNC("[Force Assert] wakeup consys (%d)\n", i);
stp_dbg_poll_cpupcr(5 , 1 , 1);
osal_sleep_ms(5);
i++;
if(i > 20){
i = 0;
break;
}
} while(1);
#endif
if(0 != mtk_wcn_stp_coredump_start_get()){
status = 0;
break;
}
j++;
if(j > 8) {
j = 0;
break;
}
} while(1);
return status;
}
static INT32 _stp_set_dump_info(ENUM_EMI_CTRL_STATE_OFFSET offset,UINT32 value)
{
UINT8 * p_virtual_addr = NULL;
p_virtual_addr = wmt_plat_get_emi_ctrl_state_base_add(offset);
if(!p_virtual_addr)
{
STP_BTM_ERR_FUNC("get virtual address fail\n");
return -1;
}
CONSYS_REG_WRITE(p_virtual_addr,value);
return 0;
}
INT32 wmt_plat_set_host_dump_state(ENUM_HOST_DUMP_STATE state)
{
PUINT8 p_virtual_addr = NULL;
p_virtual_addr = wmt_plat_get_emi_virt_add(EXP_APMEM_CTRL_HOST_SYNC_STATE);
if (!p_virtual_addr) {
WMT_PLAT_ERR_FUNC("get virtual address fail\n");
return -1;
}
CONSYS_REG_WRITE(p_virtual_addr, state);
return 0;
}
static INT32 _stp_set_host_dump_state(ENUM_HOST_DUMP_STATE state)
{
UINT8 * p_virtual_addr = NULL;
p_virtual_addr = wmt_plat_get_emi_ctrl_state_base_add(EXP_APMEM_CTRL_HOST_SYNC_STATE);
if(!p_virtual_addr)
{
STP_BTM_ERR_FUNC("get virtual address fail\n");
return -1;
}
CONSYS_REG_WRITE(p_virtual_addr, state);
return 0;
}
INT32 wmt_plat_update_host_sync_num(VOID)
{
PUINT8 p_virtual_addr = NULL;
UINT32 sync_num = 0;
p_virtual_addr = wmt_plat_get_emi_virt_add(EXP_APMEM_CTRL_HOST_SYNC_NUM);
if (!p_virtual_addr) {
WMT_PLAT_ERR_FUNC("get virtual address fail\n");
return -1;
}
sync_num = CONSYS_REG_READ(p_virtual_addr);
CONSYS_REG_WRITE(p_virtual_addr, sync_num + 1);
return 0;
}
static INT32 _stp_update_host_sync_num(VOID)
{
UINT8 * p_virtual_addr = NULL;
UINT32 sync_num = 0;
p_virtual_addr = wmt_plat_get_emi_ctrl_state_base_add(EXP_APMEM_CTRL_HOST_SYNC_NUM);
if(!p_virtual_addr)
{
STP_BTM_ERR_FUNC("get virtual address fail\n");
return -1;
}
sync_num = CONSYS_REG_READ(p_virtual_addr);
CONSYS_REG_WRITE(p_virtual_addr, sync_num + 1);
return 0;
}
INT32 mtk_wcn_consys_hw_init()
{
INT32 iRet = -1;
UINT32 addrPhy = 0;
/*set MPU for EMI share Memory*/
WMT_PLAT_INFO_FUNC("setting MPU for EMI share memory\n");
emi_mpu_set_region_protection(gConEmiPhyBase + SZ_1M/2,
gConEmiPhyBase + SZ_1M,
5,
SET_ACCESS_PERMISSON(FORBIDDEN,NO_PROTECTION,FORBIDDEN,NO_PROTECTION));
WMT_PLAT_INFO_FUNC("get consys start phy address(0x%x)\n",gConEmiPhyBase);
/*consys to ap emi remapping register:10001310, cal remapping address*/
addrPhy = (gConEmiPhyBase & 0xFFF00000) >> 20;
/*enable consys to ap emi remapping bit12*/
addrPhy = addrPhy | 0x1000;
CONSYS_REG_WRITE(CONSYS_EMI_MAPPING,CONSYS_REG_READ(CONSYS_EMI_MAPPING) | addrPhy);
WMT_PLAT_INFO_FUNC("CONSYS_EMI_MAPPING dump(0x%08x)\n",CONSYS_REG_READ(CONSYS_EMI_MAPPING));
#if 1
pEmibaseaddr = ioremap_nocache(gConEmiPhyBase + CONSYS_EMI_AP_PHY_OFFSET,CONSYS_EMI_MEM_SIZE);
#else
pEmibaseaddr = ioremap_nocache(CONSYS_EMI_AP_PHY_BASE,CONSYS_EMI_MEM_SIZE);
#endif
//pEmibaseaddr = ioremap_nocache(0x80090400,270*KBYTE);
if(pEmibaseaddr)
{
WMT_PLAT_INFO_FUNC("EMI mapping OK(0x%p)\n",pEmibaseaddr);
memset(pEmibaseaddr,0,CONSYS_EMI_MEM_SIZE);
iRet = 0;
}else{
WMT_PLAT_ERR_FUNC("EMI mapping fail\n");
}
WMT_PLAT_INFO_FUNC("register connsys restore cb for complying with IPOH function\n");
register_swsusp_restore_noirq_func(ID_M_CONNSYS,mtk_wcn_consys_hw_restore,NULL);
return iRet;
}
INT32 mtk_wcn_consys_hw_reg_ctrl(UINT32 on,UINT32 co_clock_en)
{
INT32 iRet = -1;
UINT32 retry = 10;
UINT32 consysHwChipId = 0;
WMT_PLAT_INFO_FUNC("CONSYS-HW-REG-CTRL(0x%08x),start\n",on);
if(on)
{
#if CONSYS_PMIC_CTRL_ENABLE
/*need PMIC driver provide new API protocol before 1/18/2013*/
/*1.Power on MT6323 VCN_1V8 LDO<--<VCN_1V8>-->write 0 to 0x512[1], write 1 to 0x512[14]*/
upmu_set_vcn_1v8_lp_mode_set(0);
//upmu_set_rg_vcn_1v8_en(1);
/*will be replaced by hwpoweron just as below*/
hwPowerOn(MT6323_POWER_LDO_VCN_1V8,VOL_DEFAULT,"MOD_WMT");
if(co_clock_en)
{
/*2.set VCN_28 to SW control mode<--<VCN28_ON_CTRL>-->write 0 to 0x41C[14]*/
upmu_set_vcn28_on_ctrl(0);
}
else
{
/*2.1.switch VCN28 to HW control mode<--<VCN28_ON_CTRL>-->write 1 to 0x41C[14]*/
upmu_set_vcn28_on_ctrl(1);
/*2.2.turn on VCN28LDO<--<RG_VCN28_EN>-->write 1 to 0x41C[12]*/
//upmu_set_rg_vcn28_en(1);
/*will be replaced by hwpoweron just as below*/
hwPowerOn(MT6323_POWER_LDO_VCN28,VOL_DEFAULT,"MOD_WMT");
}
#endif
/*mask this action and put it into FW patch for resolve ALPS00544691*/
#if 0
/*1.assert CONSYS CPU SW reset, <CONSYS_CPU_SW_RST_REG>, [12] = 1'b1, [31:24]=8'h88(key)--> CONSYS_CPU_SW_RST_BIT | CONSYS_CPU_SW_RST_CTRL_KEY*/
CONSYS_SET_BIT(CONSYS_CPU_SW_RST_REG, CONSYS_CPU_SW_RST_BIT | CONSYS_CPU_SW_RST_CTRL_KEY);
WMT_PLAT_DBG_FUNC("reg uump:CONSYS_CPU_SW_RST_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_CPU_SW_RST_REG));
#endif
#if 0
/*turn on top clock gating enable*/
CONSYS_REG_WRITE(CONSYS_TOP_CLKCG_CLR_REG,CONSYS_REG_READ(CONSYS_TOP_CLKCG_CLR_REG) | CONSYS_TOP_CLKCG_BIT);
WMT_PLAT_DBG_FUNC("reg dump:CONSYS_TOP_CLKCG_CLR_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_TOP_CLKCG_CLR_REG));
/*turn on SPM clock gating enable*/
CONSYS_REG_WRITE(CONSYS_PWRON_CONFG_EN_REG, CONSYS_PWRON_CONFG_EN_VALUE);
WMT_PLAT_DBG_FUNC("reg dump:CONSYS_PWRON_CONFG_EN_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_PWRON_CONFG_EN_REG));
#endif
/*use colck manger API to control MTCMOS*/
conn_power_on();
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_PWR_CONN_ACK_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_REG));
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_PWR_CONN_ACK_S_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_S_REG));
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_TOP1_PWR_CTRL_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG));
/*11.delay 10us, 26M is ready*/
udelay(10);
enable_clock(MT_CG_INFRA_CONNMCU, "WMT_MOD");
/*12.poll CONSYS CHIP until MT6582/MT6572 is returned, <CONSYS_CHIP_ID_REG>, 32'h6582/32'h6572 */
/*what does HW do, why we need to polling this register?*/
while (retry-- > 0)
{
WMT_PLAT_DBG_FUNC("CONSYS_CHIP_ID_REG(0x%08x)",CONSYS_REG_READ(CONSYS_CHIP_ID_REG));
consysHwChipId = CONSYS_REG_READ(CONSYS_CHIP_ID_REG);
if((consysHwChipId == 0x6582) || (consysHwChipId == 0x6572))
{
WMT_PLAT_INFO_FUNC("retry(%d)consys chipId(0x%08x)\n", retry,consysHwChipId);
break;
}
msleep(20);
}
/*mask this action and put it into FW patch for resolve ALPS00544691*/
#if 0
/*13.{default no need}update ROMDEL/PATCH RAM DELSEL if needed, <CONSYS_ROM_RAM_DELSEL_REG>*/
/*14.write 1 to conn_mcu_config ACR[1] if real speed MBIST (default write "1"), <CONSYS_MCU_CFG_ACR_REG>,[18]1'b1-->CONSYS_MCU_CFG_ACR_MBIST_BIT*/
/*if this bit is 0, HW will do memory auto test under low CPU frequence (26M Hz)*/
/*if this bit is 0, HW will do memory auto test under high CPU frequence(138M Hz) inclulding low CPU frequence*/
CONSYS_SET_BIT(CONSYS_MCU_CFG_ACR_REG, CONSYS_MCU_CFG_ACR_MBIST_BIT);
/*15.{default no need, Analog HW will inform if this need to be update or not 1 week after IC sample back}
update ANA_WBG(AFE) CR if needed, CONSYS_AFE_REG */
CONSYS_REG_WRITE(CONSYS_AFE_REG_DIG_RCK_01,CONSYS_AFE_REG_DIG_RCK_01_VALUE);
CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_PLL_02,CONSYS_AFE_REG_WBG_PLL_02_VALUE);
CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_WB_TX_01,CONSYS_AFE_REG_WBG_WB_TX_01_VALUE);
/*16.deassert CONSYS CPU SW reset, <CONSYS_CPU_SW_RST_REG>, [12] = 1'b0, [31:24]=8'h88(key)*/
CONSYS_CLR_BIT_WITH_KEY(CONSYS_CPU_SW_RST_REG, CONSYS_CPU_SW_RST_BIT , CONSYS_CPU_SW_RST_CTRL_KEY);
#endif
msleep(5);
iRet = 0;
}else{
disable_clock(MT_CG_INFRA_CONNMCU, "WMT_MOD");
/*New: use colck manger API to control MTCMOS*/
conn_power_off();
#if CONSYS_PMIC_CTRL_ENABLE
/*set VCN_28 to SW control mode*/
upmu_set_vcn28_on_ctrl(0);
/*turn off VCN28 LDO*/
//upmu_set_rg_vcn28_en(0);
/*will be replaced by hwPowerOff*/
hwPowerDown(MT6323_POWER_LDO_VCN28,"MOD_WMT");
/*power off MT6627 VWCN_1V8 LDO*/
upmu_set_vcn_1v8_lp_mode_set(0);
//upmu_set_rg_vcn_1v8_en(0);
/*will be replaced by hwPowerOff*/
hwPowerDown(MT6323_POWER_LDO_VCN_1V8,"MOD_WMT");
#endif
iRet = 0;
}
WMT_PLAT_INFO_FUNC("CONSYS-HW-REG-CTRL(0x%08x),finish\n",on);
return iRet;
}
INT32 mtk_wcn_consys_hw_reg_ctrl(UINT32 on, UINT32 co_clock_type)
{
INT32 iRet = -1;
UINT32 retry = 10;
UINT32 consysHwChipId = 0;
WMT_PLAT_WARN_FUNC("CONSYS-HW-REG-CTRL(0x%08x),start\n", on);
if (on) {
WMT_PLAT_DBG_FUNC("++\n");
/*step1.PMIC ctrl*/
#if CONSYS_PMIC_CTRL_ENABLE
/*need PMIC driver provide new API protocol */
/*1.AP power on VCN_1V8 LDO (with PMIC_WRAP API) VCN_1V8 */
pmic_set_register_value(PMIC_RG_VCN18_ON_CTRL, 0);
/* VOL_DEFAULT, VOL_1200, VOL_1300, VOL_1500, VOL_1800... */
#if defined(CONFIG_MTK_PMIC_LEGACY)
hwPowerOn(MT6328_POWER_LDO_VCN18, VOL_1800, "wcn_drv");
#else
if (reg_VCN18) {
regulator_set_voltage(reg_VCN18, VOL_1800, VOL_1800);
if (regulator_enable(reg_VCN18))
WMT_PLAT_ERR_FUNC("enable VCN18 fail\n");
else
WMT_PLAT_DBG_FUNC("enable VCN18 ok\n");
}
#endif
udelay(150);
if (co_clock_type) {
/*step0,clk buf ctrl */
WMT_PLAT_INFO_FUNC("co clock type(%d),turn on clk buf\n", co_clock_type);
#if CONSYS_CLOCK_BUF_CTRL
clk_buf_ctrl(CLK_BUF_CONN, 1);
#endif
/*if co-clock mode: */
/*2.set VCN28 to SW control mode (with PMIC_WRAP API) */
/*turn on VCN28 LDO only when FMSYS is activated" */
pmic_set_register_value(PMIC_RG_VCN28_ON_CTRL, 0);
} else {
/*if NOT co-clock: */
/*2.1.switch VCN28 to HW control mode (with PMIC_WRAP API) */
pmic_set_register_value(PMIC_RG_VCN28_ON_CTRL, 1);
/*2.2.turn on VCN28 LDO (with PMIC_WRAP API)" */
/*fix vcn28 not balance warning */
#if defined(CONFIG_MTK_PMIC_LEGACY)
hwPowerOn(MT6328_POWER_LDO_VCN28, VOL_2800, "wcn_drv");
#else
if (reg_VCN28) {
regulator_set_voltage(reg_VCN28, VOL_2800, VOL_2800);
if (regulator_enable(reg_VCN28))
WMT_PLAT_ERR_FUNC("enable VCN_2V8 fail!\n");
else
WMT_PLAT_DBG_FUNC("enable VCN_2V8 ok\n");
}
#endif
}
#endif
/*step2.MTCMOS ctrl*/
#ifdef CONFIG_OF /*use DT */
/*3.assert CONNSYS CPU SW reset 0x10007018 "[12]=1'b1 [31:24]=8'h88 (key)" */
CONSYS_REG_WRITE((conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET),
CONSYS_REG_READ(conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET) |
CONSYS_CPU_SW_RST_BIT | CONSYS_CPU_SW_RST_CTRL_KEY);
/*turn on SPM clock gating enable PWRON_CONFG_EN 0x10006000 32'h0b160001 */
CONSYS_REG_WRITE((conn_reg.spm_base + CONSYS_PWRON_CONFG_EN_OFFSET), CONSYS_PWRON_CONFG_EN_VALUE);
#if CONSYS_PWR_ON_OFF_API_AVAILABLE
#if defined(CONFIG_MTK_CLKMGR)
iRet = conn_power_on(); /* consult clkmgr owner. */
if (iRet)
WMT_PLAT_ERR_FUNC("conn_power_on fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("conn_power_on ok\n");
#else
iRet = clk_prepare_enable(clk_scp_conn_main);
if (iRet)
WMT_PLAT_ERR_FUNC("clk_prepare_enable(clk_scp_conn_main) fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("clk_prepare_enable(clk_scp_conn_main) ok\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#else
/*2.write conn_top1_pwr_on=1, power on conn_top1 0x10006280 [2] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) |
CONSYS_SPM_PWR_ON_BIT);
/*3.read conn_top1_pwr_on_ack =1, power on ack ready 0x1000660C [1] */
while (0 == (CONSYS_PWR_ON_ACK_BIT & CONSYS_REG_READ(conn_reg.spm_base + CONSYS_PWR_CONN_ACK_OFFSET)))
NULL;
/*5.write conn_top1_pwr_on_s=1, power on conn_top1 0x10006280 [3] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) |
CONSYS_SPM_PWR_ON_S_BIT);
/*6.write conn_clk_dis=0, enable connsys clock 0x10006280 [4] 1'b0 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) &
~CONSYS_CLK_CTRL_BIT);
/*7.wait 1us */
udelay(1);
/*8.read conn_top1_pwr_on_ack_s =1, power on ack ready 0x10006610 [1] */
while (0 == (CONSYS_PWR_CONN_ACK_S_BIT &
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_PWR_CONN_ACK_S_OFFSET)))
NULL;
/*9.release connsys ISO, conn_top1_iso_en=0 0x10006280 [1] 1'b0 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) &
~CONSYS_SPM_PWR_ISO_S_BIT);
/*10.release SW reset of connsys, conn_ap_sw_rst_b=1 0x10006280[0] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) |
CONSYS_SPM_PWR_RST_BIT);
/*disable AXI BUS protect */
CONSYS_REG_WRITE(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_EN_OFFSET,
CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_EN_OFFSET) &
~CONSYS_PROT_MASK);
while (CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_STA1_OFFSET) & CONSYS_PROT_MASK)
NULL;
#endif
/*11.26M is ready now, delay 10us for mem_pd de-assert */
udelay(10);
/*enable AP bus clock : connmcu_bus_pd API: enable_clock() ++?? */
#if CONSYS_AHB_CLK_MAGEMENT
#if defined(CONFIG_MTK_CLKMGR)
enable_clock(MT_CG_INFRA_CONNMCU_BUS, "WCN_MOD");
WMT_PLAT_DBG_FUNC("enable MT_CG_INFRA_CONNMCU_BUS CLK\n");
#else
iRet = clk_prepare_enable(clk_infra_conn_main);
if (iRet)
WMT_PLAT_ERR_FUNC("clk_prepare_enable(clk_infra_conn_main) fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("[CCF]enable clk_infra_conn_main\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#endif
/*12.poll CONNSYS CHIP ID until chipid is returned 0x18070008 */
while (retry-- > 0) {
consysHwChipId = CONSYS_REG_READ(conn_reg.mcu_base + CONSYS_CHIP_ID_OFFSET);
if ((consysHwChipId == 0x0321) || (consysHwChipId == 0x0335) || (consysHwChipId == 0x0337)) {
WMT_PLAT_INFO_FUNC("retry(%d)consys chipId(0x%08x)\n", retry, consysHwChipId);
break;
}
WMT_PLAT_ERR_FUNC("Read CONSYS chipId(0x%08x)", consysHwChipId);
msleep(20);
}
if ((0 == retry) || (0 == consysHwChipId)) {
WMT_PLAT_ERR_FUNC("Maybe has a consys power on issue,(0x%08x)\n", consysHwChipId);
WMT_PLAT_ERR_FUNC("reg dump:CONSYS_CPU_SW_RST_REG(0x%x)\n",
CONSYS_REG_READ(conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET));
WMT_PLAT_ERR_FUNC("reg dump:CONSYS_PWR_CONN_ACK_REG(0x%x)\n",
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_PWR_CONN_ACK_OFFSET));
WMT_PLAT_ERR_FUNC("reg dump:CONSYS_PWR_CONN_ACK_S_REG(0x%x)\n",
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_PWR_CONN_ACK_S_OFFSET));
WMT_PLAT_ERR_FUNC("reg dump:CONSYS_TOP1_PWR_CTRL_REG(0x%x)\n",
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET));
}
/*13.{default no need}update ROMDEL/PATCH RAM DELSEL if needed 0x18070114 */
/*
*14.write 1 to conn_mcu_confg ACR[1] if real speed MBIST
*(default write "1") ACR 0x18070110[18] 1'b1
*if this bit is 0, HW will do memory auto test under low CPU frequence (26M Hz)
*if this bit is 0, HW will do memory auto test under high CPU frequence(138M Hz)
*inclulding low CPU frequence
*/
CONSYS_REG_WRITE(conn_reg.mcu_base + CONSYS_MCU_CFG_ACR_OFFSET,
CONSYS_REG_READ(conn_reg.mcu_base + CONSYS_MCU_CFG_ACR_OFFSET) |
CONSYS_MCU_CFG_ACR_MBIST_BIT);
#if 0
/*15.default no need,update ANA_WBG(AFE) CR if needed, CONSYS_AFE_REG */
CONSYS_REG_WRITE(CONSYS_AFE_REG_DIG_RCK_01, CONSYS_AFE_REG_DIG_RCK_01_VALUE);
CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_PLL_02, CONSYS_AFE_REG_WBG_PLL_02_VALUE);
CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_WB_TX_01, CONSYS_AFE_REG_WBG_WB_TX_01_VALUE);
#endif
/*16.deassert CONNSYS CPU SW reset 0x10007018 "[12]=1'b0 [31:24] =8'h88 (key)" */
CONSYS_REG_WRITE(conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET,
(CONSYS_REG_READ(conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET) &
~CONSYS_CPU_SW_RST_BIT) | CONSYS_CPU_SW_RST_CTRL_KEY);
#else /*use HADRCODE, maybe no use.. */
/*3.assert CONNSYS CPU SW reset 0x10007018 "[12]=1'b1 [31:24]=8'h88 (key)" */
CONSYS_REG_WRITE(CONSYS_CPU_SW_RST_REG,
(CONSYS_REG_READ(CONSYS_CPU_SW_RST_REG) | CONSYS_CPU_SW_RST_BIT |
CONSYS_CPU_SW_RST_CTRL_KEY));
/*turn on SPM clock gating enable PWRON_CONFG_EN 0x10006000 32'h0b160001 */
CONSYS_REG_WRITE(CONSYS_PWRON_CONFG_EN_REG, CONSYS_PWRON_CONFG_EN_VALUE);
#if CONSYS_PWR_ON_OFF_API_AVAILABLE
#if defined(CONFIG_MTK_CLKMGR)
iRet = conn_power_on(); /* consult clkmgr owner */
if (iRet)
WMT_PLAT_ERR_FUNC("conn_power_on fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("conn_power_on ok\n");
#else
iRet = clk_prepare_enable(clk_scp_conn_main);
if (iRet)
WMT_PLAT_ERR_FUNC("clk_prepare_enable(clk_scp_conn_main) fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("clk_prepare_enable(clk_scp_conn_main) ok\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#else
/*2.write conn_top1_pwr_on=1, power on conn_top1 0x10006280 [2] 1'b1 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_SPM_PWR_ON_BIT);
/*3.read conn_top1_pwr_on_ack =1, power on ack ready 0x1000660C [1] */
while (0 == (CONSYS_PWR_ON_ACK_BIT & CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_REG)))
NULL;
/*5.write conn_top1_pwr_on_s=1, power on conn_top1 0x10006280 [3] 1'b1 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_SPM_PWR_ON_S_BIT);
/*6.write conn_clk_dis=0, enable connsys clock 0x10006280 [4] 1'b0 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) & ~CONSYS_CLK_CTRL_BIT);
/*7.wait 1us */
udelay(1);
/*8.read conn_top1_pwr_on_ack_s =1, power on ack ready 0x10006610 [1] */
while (0 == (CONSYS_PWR_CONN_ACK_S_BIT & CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_S_REG)))
NULL;
/*9.release connsys ISO, conn_top1_iso_en=0 0x10006280 [1] 1'b0 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) & ~CONSYS_SPM_PWR_ISO_S_BIT);
/*10.release SW reset of connsys, conn_ap_sw_rst_b=1 0x10006280[0] 1'b1 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_SPM_PWR_RST_BIT);
/*disable AXI BUS protect */
CONSYS_REG_WRITE(CONSYS_TOPAXI_PROT_EN, CONSYS_REG_READ(CONSYS_TOPAXI_PROT_EN) & ~CONSYS_PROT_MASK);
while (CONSYS_REG_READ(CONSYS_TOPAXI_PROT_STA1) & CONSYS_PROT_MASK)
NULL;
#endif
/*11.26M is ready now, delay 10us for mem_pd de-assert */
udelay(10);
/*enable AP bus clock : connmcu_bus_pd API: enable_clock() ++?? */
#if CONSYS_AHB_CLK_MAGEMENT
#if defined(CONFIG_MTK_CLKMGR)
enable_clock(MT_CG_INFRA_CONNMCU_BUS, "WCN_MOD");
WMT_PLAT_DBG_FUNC("enable MT_CG_INFRA_CONNMCU_BUS CLK\n");
#else
iRet = clk_prepare_enable(clk_infra_conn_main);
if (iRet)
WMT_PLAT_ERR_FUNC("clk_prepare_enable(clk_infra_conn_main) fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("[CCF]enable clk_infra_conn_main\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#endif
/*12.poll CONNSYS CHIP ID until 6752 is returned 0x18070008 32'h6752 */
while (retry-- > 0) {
WMT_PLAT_DBG_FUNC("CONSYS_CHIP_ID_REG(0x%08x)", CONSYS_REG_READ(CONSYS_CHIP_ID_REG));
consysHwChipId = CONSYS_REG_READ(CONSYS_CHIP_ID_REG);
if ((consysHwChipId == 0x0321) || (consysHwChipId == 0x0335) || (consysHwChipId == 0x0337)) {
WMT_PLAT_INFO_FUNC("retry(%d)consys chipId(0x%08x)\n", retry, consysHwChipId);
break;
}
msleep(20);
}
if ((0 == retry) || (0 == consysHwChipId)) {
WMT_PLAT_ERR_FUNC("Maybe has a consys power on issue,(0x%08x)\n", consysHwChipId);
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_CPU_SW_RST_REG(0x%x)\n",
CONSYS_REG_READ(CONSYS_CPU_SW_RST_REG));
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_PWR_CONN_ACK_REG(0x%x)\n",
CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_REG));
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_PWR_CONN_ACK_S_REG(0x%x)\n",
CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_S_REG));
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_TOP1_PWR_CTRL_REG(0x%x)\n",
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG));
}
/*13.{default no need}update ROMDEL/PATCH RAM DELSEL if needed 0x18070114 */
/*
*14.write 1 to conn_mcu_confg ACR[1] if real speed MBIST
*(default write "1") ACR 0x18070110[18] 1'b1
*if this bit is 0, HW will do memory auto test under low CPU frequence (26M Hz)
*if this bit is 0, HW will do memory auto test under high CPU frequence(138M Hz)
*inclulding low CPU frequence
*/
CONSYS_REG_WRITE(CONSYS_MCU_CFG_ACR_REG,
CONSYS_REG_READ(CONSYS_MCU_CFG_ACR_REG) | CONSYS_MCU_CFG_ACR_MBIST_BIT);
/*update ANA_WBG(AFE) CR. AFE setting file: AP Offset = 0x180B2000 */
#if 0
/*15.default no need,update ANA_WBG(AFE) CR if needed, CONSYS_AFE_REG */
CONSYS_REG_WRITE(CONSYS_AFE_REG_DIG_RCK_01, CONSYS_AFE_REG_DIG_RCK_01_VALUE);
CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_PLL_02, CONSYS_AFE_REG_WBG_PLL_02_VALUE);
CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_WB_TX_01, CONSYS_AFE_REG_WBG_WB_TX_01_VALUE);
#endif
/*16.deassert CONNSYS CPU SW reset 0x10007018 "[12]=1'b0 [31:24] =8'h88(key)" */
CONSYS_REG_WRITE(CONSYS_CPU_SW_RST_REG,
(CONSYS_REG_READ(CONSYS_CPU_SW_RST_REG) & ~CONSYS_CPU_SW_RST_BIT) |
CONSYS_CPU_SW_RST_CTRL_KEY);
#endif
msleep(20); /* msleep < 20ms can sleep for up to 20ms */
} else {
#ifdef CONFIG_OF
#if CONSYS_AHB_CLK_MAGEMENT
#if defined(CONFIG_MTK_CLKMGR)
disable_clock(MT_CG_INFRA_CONNMCU_BUS, "WMT_MOD");
#else
clk_disable_unprepare(clk_infra_conn_main);
WMT_PLAT_DBG_FUNC("[CCF] clk_disable_unprepare(clk_infra_conn_main) calling\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#endif
#if CONSYS_PWR_ON_OFF_API_AVAILABLE
#if defined(CONFIG_MTK_CLKMGR)
/*power off connsys by API (MT6582, MT6572 are different) API: conn_power_off() */
iRet = conn_power_off(); /* consult clkmgr owner */
if (iRet)
WMT_PLAT_ERR_FUNC("conn_power_off fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("conn_power_off ok\n");
#else
clk_disable_unprepare(clk_scp_conn_main);
WMT_PLAT_DBG_FUNC("clk_disable_unprepare(clk_scp_conn_main) calling\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#else
{
INT32 count = 0;
CONSYS_REG_WRITE(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_EN_OFFSET,
CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_EN_OFFSET) |
CONSYS_PROT_MASK);
while ((CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_STA1_OFFSET) &
CONSYS_PROT_MASK) != CONSYS_PROT_MASK) {
count++;
if (count > 1000)
break;
}
}
/*release connsys ISO, conn_top1_iso_en=1 0x10006280 [1] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) |
CONSYS_SPM_PWR_ISO_S_BIT);
/*assert SW reset of connsys, conn_ap_sw_rst_b=0 0x10006280[0] 1'b0 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) &
~CONSYS_SPM_PWR_RST_BIT);
/*write conn_clk_dis=1, disable connsys clock 0x10006280 [4] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) |
CONSYS_CLK_CTRL_BIT);
/*wait 1us */
udelay(1);
/*write conn_top1_pwr_on=0, power off conn_top1 0x10006280 [3:2] 2'b00 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) &
~(CONSYS_SPM_PWR_ON_BIT | CONSYS_SPM_PWR_ON_S_BIT));
#endif
#else
#if CONSYS_PWR_ON_OFF_API_AVAILABLE
#if CONSYS_AHB_CLK_MAGEMENT
#if defined(CONFIG_MTK_CLKMGR)
disable_clock(MT_CG_INFRA_CONNMCU_BUS, "WMT_MOD");
#else
clk_disable_unprepare(clk_infra_conn_main);
#endif /* defined(CONFIG_MTK_CLKMGR) */
#endif
#if defined(CONFIG_MTK_CLKMGR)
/*power off connsys by API: conn_power_off() */
iRet = conn_power_off(); /* consult clkmgr owner */
if (iRet)
WMT_PLAT_ERR_FUNC("conn_power_off fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("conn_power_off ok\n");
#else
clk_disable_unprepare(clk_scp_conn_main);
WMT_PLAT_DBG_FUNC("clk_disable_unprepare(clk_scp_conn_main) calling\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#else
{
INT32 count = 0;
CONSYS_REG_WRITE(CONSYS_TOPAXI_PROT_EN,
CONSYS_REG_READ(CONSYS_TOPAXI_PROT_EN) | CONSYS_PROT_MASK);
while ((CONSYS_REG_READ(CONSYS_TOPAXI_PROT_STA1) & CONSYS_PROT_MASK) != CONSYS_PROT_MASK) {
count++;
if (count > 1000)
break;
}
}
/*release connsys ISO, conn_top1_iso_en=1 0x10006280 [1] 1'b1 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_SPM_PWR_ISO_S_BIT);
/*assert SW reset of connsys, conn_ap_sw_rst_b=0 0x10006280[0] 1'b0 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) & ~CONSYS_SPM_PWR_RST_BIT);
/*write conn_clk_dis=1, disable connsys clock 0x10006280 [4] 1'b1 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_CLK_CTRL_BIT);
/*wait 1us */
udelay(1);
/*write conn_top1_pwr_on=0, power off conn_top1 0x10006280 [3:2] 2'b00 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG, CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) &
~(CONSYS_SPM_PWR_ON_BIT | CONSYS_SPM_PWR_ON_S_BIT));
#endif
#endif
#if CONSYS_PMIC_CTRL_ENABLE
if (co_clock_type) {
/*VCN28 has been turned off by GPS OR FM */
#if CONSYS_CLOCK_BUF_CTRL
clk_buf_ctrl(CLK_BUF_CONN, 0);
#endif
} else {
pmic_set_register_value(PMIC_RG_VCN28_ON_CTRL, 0);
/*turn off VCN28 LDO (with PMIC_WRAP API)" */
#if defined(CONFIG_MTK_PMIC_LEGACY)
hwPowerDown(MT6328_POWER_LDO_VCN28, "wcn_drv");
#else
if (reg_VCN28) {
if (regulator_disable(reg_VCN28))
WMT_PLAT_ERR_FUNC("disable VCN_2V8 fail!\n");
else
WMT_PLAT_DBG_FUNC("disable VCN_2V8 ok\n");
}
#endif
}
/*AP power off MT6625L VCN_1V8 LDO */
pmic_set_register_value(PMIC_RG_VCN18_ON_CTRL, 0);
#if defined(CONFIG_MTK_PMIC_LEGACY)
hwPowerDown(MT6328_POWER_LDO_VCN18, "wcn_drv");
#else
if (reg_VCN18) {
if (regulator_disable(reg_VCN18))
WMT_PLAT_ERR_FUNC("disable VCN_1V8 fail!\n");
else
WMT_PLAT_DBG_FUNC("disable VCN_1V8 ok\n");
}
#endif
#endif
}
WMT_PLAT_WARN_FUNC("CONSYS-HW-REG-CTRL(0x%08x),finish\n", on);
return 0;
}
INT32 mtk_wcn_consys_hw_reg_ctrl(UINT32 on,UINT32 co_clock_en)
{
#if PWR_ON_OFF_API_AVALIABLE
INT32 iRet = -1;
#endif
UINT32 retry = 10;
UINT32 consysHwChipId = 0;
WMT_PLAT_INFO_FUNC("CONSYS-HW-REG-CTRL(0x%08x),start\n",on);
WMT_PLAT_DBG_FUNC("CONSYS_EMI_MAPPING dump before power on/off(0x%08x)\n",CONSYS_REG_READ(CONSYS_EMI_MAPPING));
if(on)
{
#if CONSYS_PMIC_CTRL_ENABLE
/*need PMIC driver provide new API protocol */
/*1.AP power on MT6325 VCN_1V8 LDO (with PMIC_WRAP API) VCN_1V8 "0x0512[1] "1'b0 0x0512[14]" 1'b1"*/
mt6325_upmu_set_rg_vcn18_on_ctrl(0);
/* VOL_DEFAULT, VOL_1200, VOL_1300, VOL_1500, VOL_1800, VOL_2500, VOL_2800, VOL_3000, VOL_3300*/
hwPowerOn(MT6325_POWER_LDO_VCN18, VOL_1800, "wcn_drv");
udelay(150);
if(co_clock_en)
{
/*if co-clock mode:*/
/*2.set VCN28 to SW control mode (with PMIC_WRAP API) VCN28_ON_CTRL 0x041C[14] 1'b0*/
/*turn on VCN28 LDO only when FMSYS is activated" */
mt6325_upmu_set_rg_vcn28_on_ctrl(0);
}
else
{
/*if NOT co-clock:*/
/*2.1.switch VCN28 to HW control mode (with PMIC_WRAP API) VCN28_ON_CTRL 0x041C[14] 1'b1*/
mt6325_upmu_set_rg_vcn28_on_ctrl(1);
/*2.2.turn on VCN28 LDO (with PMIC_WRAP API)" RG_VCN28_EN" 0x041C[12] 1'b1 */
hwPowerOn(MT6325_POWER_LDO_VCN28, VOL_2800, "wcn_drv");
}
#endif
/*3.assert CONNSYS CPU SW reset 0x10007018 "[12]=1'b1 [31:24]=8'h88 (key)"*/
CONSYS_REG_WRITE(CONSYS_CPU_SW_RST_REG, (CONSYS_REG_READ(CONSYS_CPU_SW_RST_REG) | CONSYS_CPU_SW_RST_BIT | CONSYS_CPU_SW_RST_CTRL_KEY));
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_CPU_SW_RST_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_CPU_SW_RST_REG));
/*turn on top clock gating enable TOP_CLKCG_CLR 0x10000084[26] 1'b1 */
CONSYS_REG_WRITE(CONSYS_TOP_CLKCG_CLR_REG,CONSYS_REG_READ(CONSYS_TOP_CLKCG_CLR_REG) | CONSYS_TOP_CLKCG_BIT);
/*turn on SPM clock gating enable PWRON_CONFG_EN 0x10006000 32'h0b160001 */
CONSYS_REG_WRITE(CONSYS_PWRON_CONFG_EN_REG, CONSYS_PWRON_CONFG_EN_VALUE);
#if PWR_ON_OFF_API_AVALIABLE
iRet = conn_power_on(); //consult clkmgr owner
if(iRet)
{
WMT_PLAT_ERR_FUNC("conn_power_on fail(%d)\n",iRet);
}else
{
WMT_PLAT_INFO_FUNC("conn_power_on ok\n");
}
#else
/*2.write conn_top1_pwr_on=1, power on conn_top1 (MT6572 with the same addr) conn_spm_pwr_on 0x10006280 [2] 1'b1 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG, CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_SPM_PWR_ON_BIT);
/*3.read conn_top1_pwr_on_ack =1, power on ack ready (MT6572 with the same addr) pwr_conn_ack 0x1000660C [1] */
while (0 == (CONSYS_PWR_ON_ACK_BIT & CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_REG)));
/*4.write conn_top1_mem_PD=0, power on MCU memory (MT6572 with the same addr) sram_conn_pd 0x10006280 [8] 1'b1 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG, CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_SRAM_CONN_PD_BIT);
/*5.write conn_top1_pwr_on_s=1, power on conn_top1 (MT6572 with the same addr) conn_spm_pwr_on_s 0x10006280 [3] 1'b1 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG, CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_SPM_PWR_ON_S_BIT);
/*6.write conn_clk_dis=0, enable connsys clock (MT6572 with the same addr) conn_clk_dis 0x10006280 [4] 1'b0 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG, CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) & ~CONSYS_CLK_CTRL_BIT);
/*7.wait 1us */
udelay(1);
/*8.read conn_top1_pwr_on_ack_s =1, power on ack ready (MT6572 with the same addr) pwr_conn_ack_s 0x10006610 [1] */
while (0 == (CONSYS_PWR_CONN_ACK_S_BIT & CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_S_REG)));
/*9.release connsys ISO, conn_top1_iso_en=0 (MT6572 with the same addr) conn_spm_pwr_iso 0x10006280 [1] 1'b0 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG, CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) & ~CONSYS_SPM_PWR_ISO_S_BIT);
/*10.release SW reset of connsys, conn_ap_sw_rst_b=1 (MT6572 with the same addr) conn_spm_pwr_rst_b 0x10006280[0] 1'b1 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG, CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_SPM_PWR_RST_BIT);
#endif
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_PWR_CONN_ACK_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_REG));
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_PWR_CONN_ACK_S_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_S_REG));
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_TOP1_PWR_CTRL_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG));
/*11.26M is ready now, delay 10us for mem_pd de-assert*/
udelay(10);
/*enable AP bus clock : connmcu_bus_pd API: enable_clock() ++??*/
/*12.poll CONNSYS CHIP ID until 6580 is returned 0x18070008 32'h6752 */
while (retry-- > 0)
{
WMT_PLAT_DBG_FUNC("CONSYS_CHIP_ID_REG(0x%08x)",CONSYS_REG_READ(CONSYS_CHIP_ID_REG));
consysHwChipId = CONSYS_REG_READ(CONSYS_CHIP_ID_REG);
if(consysHwChipId == 0x6580)
{
WMT_PLAT_INFO_FUNC("retry(%d)consys chipId(0x%08x)\n", retry,consysHwChipId);
break;
}
msleep(20);
}
/*13.{default no need}update ROMDEL/PATCH RAM DELSEL if needed 0x18070114 "[3:0] ROM DELSEL [7:$] RAM4Kx32 DELSEL" ??*/
/*14.write 1 to conn_mcu_confg ACR[1] if real speed MBIST (default write "1") ACR 0x18070110[18] 1'b1*/
/*if this bit is 0, HW will do memory auto test under low CPU frequence (26M Hz)*/
/*if this bit is 0, HW will do memory auto test under high CPU frequence(138M Hz) inclulding low CPU frequence*/
CONSYS_REG_WRITE(CONSYS_MCU_CFG_ACR_REG, CONSYS_REG_READ(CONSYS_MCU_CFG_ACR_REG) | CONSYS_MCU_CFG_ACR_MBIST_BIT);
/*update ANA_WBG(AFE) CR. AFE setting file: MT6752_AFE_SW_patch_REG_xxxx.xlsx ??" AP Offset = 0x180B2000 ??*/
#if 0
/*15.{default no need, Analog HW will inform if this need to be update or not 1 week after IC sample back}
update ANA_WBG(AFE) CR if needed, CONSYS_AFE_REG */
CONSYS_REG_WRITE(CONSYS_AFE_REG_DIG_RCK_01,CONSYS_AFE_REG_DIG_RCK_01_VALUE);
CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_PLL_02,CONSYS_AFE_REG_WBG_PLL_02_VALUE);
CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_WB_TX_01,CONSYS_AFE_REG_WBG_WB_TX_01_VALUE);
#endif
/*16.deassert CONNSYS CPU SW reset (need to check MT6580) 0x10007018 "[12]=1'b0 [31:24] =8'h88 (key)"*/
CONSYS_REG_WRITE(CONSYS_CPU_SW_RST_REG,
(CONSYS_REG_READ(CONSYS_CPU_SW_RST_REG) & ~CONSYS_CPU_SW_RST_BIT) | CONSYS_CPU_SW_RST_CTRL_KEY);
msleep(5);
}else{
#if PWR_ON_OFF_API_AVALIABLE
WMT_PLAT_INFO_FUNC("\n conn_power_off begin\n");
/*power off connsys by API (MT6582, MT6572 are different) API: conn_power_off() */
iRet = conn_power_off();//consult clkmgr owner
WMT_PLAT_INFO_FUNC("\n conn_power_off end\n");
if(iRet)
{
WMT_PLAT_ERR_FUNC("conn_power_off fail(%d)\n",iRet);
}else
{
WMT_PLAT_INFO_FUNC("conn_power_off ok\n");
}
#else
/*assert SW reset of connsys, conn_ap_sw_rst_b=0 (MT6572 with the same addr) 0x10006280[0] 1'b0 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG, CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) & ~CONSYS_SPM_PWR_RST_BIT);
/*release connsys ISO, conn_top1_iso_en=1 (MT6572 with the same addr) 0x10006280 [1] 1'b1 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG, CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_SPM_PWR_ISO_S_BIT);
/*DA_WBG_EN_XBUF=0 */
/*wait 1us */
udelay(1);
/*write conn_top1_mem_PD=1, power off MCU memory (MT6572 with the same addr) 0x10006280 [8] 1'b0 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG, CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) & ~CONSYS_SRAM_CONN_PD_BIT);
/*write conn_top1_pwr_on=0, power off conn_top1 (MT6572 with the same addr) 0x10006280 [3:2] 2'b00 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG, CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) & ~(CONSYS_SPM_PWR_ON_BIT | CONSYS_SPM_PWR_ON_S_BIT));
/*write conn_clk_dis=1, disable connsys clock (MT6572 with the same addr) conn_clk_dis 0x10006280 [4] 1'b1 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG, CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) |CONSYS_CLK_CTRL_BIT);
#endif
#if CONSYS_PMIC_CTRL_ENABLE
/*set VCN_28 to SW control mode (with PMIC_WRAP API) "1. VCN28_ON_CTRL "0x041C[14] 1'b0*/
mt6325_upmu_set_rg_vcn28_on_ctrl(0);
/*turn off VCN28 LDO (with PMIC_WRAP API)" 2. RG_VCN28_EN" 0x041C[12]" 1'b0*/
hwPowerDown(MT6325_POWER_LDO_VCN28, "wcn_drv");
/*AP power off MT6625L VCN_1V8 LDO (with PMIC_WRAP API) "0x0512[1]1'b0 0x0512[14]" 1'b0*/
mt6325_upmu_set_rg_vcn18_mode_set(0);
hwPowerDown(MT6325_POWER_LDO_VCN18, "wcn_drv");
#endif
}
WMT_PLAT_INFO_FUNC("CONSYS-HW-REG-CTRL(0x%08x),finish\n",on);
return 0;
}
INT32 mtk_wcn_consys_hw_reg_ctrl(UINT32 on,UINT32 co_clock_en)
{
UINT32 retry = 10;
UINT32 consysHwChipId = 0;
#if PWR_ON_OFF_API_AVALIABLE
INT32 iRet = -1;
#endif
WMT_PLAT_INFO_FUNC("CONSYS-HW-REG-CTRL(0x%08x),start\n",on);
WMT_PLAT_DBG_FUNC("CONSYS_EMI_MAPPING dump before power on/off(0x%08x)\n",CONSYS_REG_READ(CONSYS_EMI_MAPPING));
if(on)
{
#if CONSYS_PMIC_CTRL_ENABLE
if(mtk_wcn_regulator_get()){
WMT_PLAT_ERR_FUNC("regulator_get fail\n");
return -1;
}
/*need PMIC driver provide new API protocol */
/*1.AP power on MT6350 VCN_1V8 LDO (with PMIC_WRAP API) VCN_1V8 0x0510[1] "1'b0 0x0512[14]" 1'b1"*/
pmic_set_register_value(PMIC_VCN_1V8_ON_CTRL,0);
if(reg_V18){
regulator_enable(reg_V18);
WMT_PLAT_INFO_FUNC("wmt_dev enable VCN_1V8\n");
}
udelay(300);
if(co_clock_en)
{
/*if co-clock mode:*/
/*2.set RF XO BUF source from CellularRF DA_XOBUF_SEL 0x1000513C[7:6] 2'b10*/
CONSYS_REG_WRITE((conn_reg.da_xobuf_base+ CONSYS_DA_XOBUF_OFFSET), CONSYS_REG_READ(conn_reg.da_xobuf_base + CONSYS_DA_XOBUF_OFFSET) & ~(0x1 << 6) );
CONSYS_REG_WRITE((conn_reg.da_xobuf_base+ CONSYS_DA_XOBUF_OFFSET), CONSYS_REG_READ(conn_reg.da_xobuf_base + CONSYS_DA_XOBUF_OFFSET) | (0x1 << 7) );
WMT_PLAT_INFO_FUNC("co_clock mode reg dump:XO BUFFER(0x%08x)\n",CONSYS_REG_READ(conn_reg.da_xobuf_base + CONSYS_DA_XOBUF_OFFSET));
}
else
{
/*if NOT co-clock:*/
/*2.1 switch VCN28 to HW control mode (with PMIC_WRAP API) RG_VCN28_ON_CTRL 0x041C[14] 1'b1*/
pmic_set_register_value(PMIC_VCN28_ON_CTRL,1);
/*2.2 turn on VCN28 LDO (with PMIC_WRAP API) DA_XOBUF_SEL 0x1000513C[7:6]" " 2'b11"*/
CONSYS_REG_WRITE((conn_reg.da_xobuf_base+ CONSYS_DA_XOBUF_OFFSET), CONSYS_REG_READ(conn_reg.da_xobuf_base + CONSYS_DA_XOBUF_OFFSET) | ((0x1 << 7) |(0x1 << 6)));
WMT_PLAT_INFO_FUNC("NOT co_clock mode reg dump:XO BUFFER(0x%08x)\n",CONSYS_REG_READ(conn_reg.da_xobuf_base + CONSYS_DA_XOBUF_OFFSET));
udelay(300);
}
#endif
/*3.assert CONNSYS CPU SW reset 0x10007018 "[12]=1'b1 [31:24]=8'h88 (key)"*/
CONSYS_REG_WRITE((conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET), CONSYS_REG_READ(conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET) | CONSYS_CPU_SW_RST_BIT | CONSYS_CPU_SW_RST_CTRL_KEY);
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_CPU_SW_RST_REG(0x%x)\n",CONSYS_REG_READ(conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET));
/*turn on top clock gating enable TOP_CLKCG_CLR 0x10000084[26] 1'b1 */
// CONSYS_REG_WRITE((conn_reg.topckgen_base + CONSYS_TOP_CLKCG_CLR_OFFSET), CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOP_CLKCG_CLR_OFFSET) | CONSYS_TOP_CLKCG_BIT);
/*turn on SPM clock gating enable PWRON_CONFG_EN 0x10006000 32'h0b160001 */
CONSYS_REG_WRITE((conn_reg.spm_base + CONSYS_PWRON_CONFG_EN_OFFSET), CONSYS_PWRON_CONFG_EN_VALUE);
#if PWR_ON_OFF_API_AVALIABLE
iRet = conn_power_on(); //consult clkmgr owner.
if(iRet)
{
WMT_PLAT_ERR_FUNC("conn_power_on fail(%d)\n",iRet);
}else
{
WMT_PLAT_INFO_FUNC("conn_power_on ok\n");
}
#else
/*2.write conn_top1_pwr_on=1, power on conn_top1 (MT6572 with the same addr) conn_spm_pwr_on 0x10006280 [2] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET, CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) | CONSYS_SPM_PWR_ON_BIT);
/*3.read conn_top1_pwr_on_ack =1, power on ack ready (MT6572 with the same addr) pwr_conn_ack 0x1000660C [1] */
while (0 == (CONSYS_PWR_ON_ACK_BIT & CONSYS_REG_READ(conn_reg.spm_base + CONSYS_PWR_CONN_ACK_OFFSET)));
/*4.write conn_top1_mem_PD=0, power on MCU memory (MT6572 with the same addr) sram_conn_pd 0x10006280 [3] 1'b1 */
//CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET, CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) | CONSYS_SRAM_CONN_PD_BIT);
/*5.write conn_top1_pwr_on_s=1, power on conn_top1 (MT6572 with the same addr) conn_spm_pwr_on_s 0x10006280 [3] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET, CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) | CONSYS_SPM_PWR_ON_S_BIT);
/*6.write conn_clk_dis=0, enable connsys clock (MT6572 with the same addr) conn_clk_dis 0x10006280 [4] 1'b0 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET, CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) & ~CONSYS_CLK_CTRL_BIT);
/*7.wait 1us */
udelay(1);
/*8.read conn_top1_pwr_on_ack_s =1, power on ack ready (MT6572 with the same addr) pwr_conn_ack_s 0x10006610 [1] */
while (0 == (CONSYS_PWR_CONN_ACK_S_BIT & CONSYS_REG_READ(conn_reg.spm_base + CONSYS_PWR_CONN_ACK_S_OFFSET)));
/*9.release connsys ISO, conn_top1_iso_en=0 (MT6572 with the same addr) conn_spm_pwr_iso 0x10006280 [1] 1'b0 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET, CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) & ~CONSYS_SPM_PWR_ISO_S_BIT);
/*10.release SW reset of connsys, conn_ap_sw_rst_b=1 (MT6572 with the same addr) conn_spm_pwr_rst_b 0x10006280[0] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET, CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) | CONSYS_SPM_PWR_RST_BIT);
/*Disable AXI bus protect 0x10001220[8] 0x10001220[9] 1'b0 1'b0*/
CONSYS_REG_WRITE(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_EN_OFFSET, CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_EN_OFFSET) & ~CONSYS_PROT_MASK);
// while (CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_STA1_OFFSET) & CONSYS_PROT_MASK) {
// }
#endif
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_PWR_CONN_ACK_REG(0x%x)\n",CONSYS_REG_READ(conn_reg.spm_base + CONSYS_PWR_CONN_ACK_OFFSET));
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_PWR_CONN_ACK_S_REG(0x%x)\n",CONSYS_REG_READ(conn_reg.spm_base + CONSYS_PWR_CONN_ACK_S_OFFSET));
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_TOP1_PWR_CTRL_REG(0x%x)\n",CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET));
/*11.26M is ready now, delay 10us for mem_pd de-assert*/
udelay(10);
/*enable AP bus clock : connmcu_bus_pd API: enable_clock() ++??*/
/*12.poll CONNSYS CHIP ID until 6580 is returned 0x18070008 32'h6580 */
while (retry-- > 0)
{
consysHwChipId = CONSYS_REG_READ(conn_reg.mcu_base + CONSYS_CHIP_ID_OFFSET);
if(consysHwChipId == 0x6580) {
WMT_PLAT_INFO_FUNC("retry(%d)consys chipId(0x%08x)\n", retry,consysHwChipId);
break;
} else {
WMT_PLAT_INFO_FUNC("Read CONSYS chipId(0x%08x)",consysHwChipId);
}
msleep(20);
}
/*13.{default no need}update ROMDEL/PATCH RAM DELSEL if needed 0x18070114 "[3:0] ROM DELSEL [7:4] RAM4Kx32 DELSEL" ??*/
/*14.write 1 to conn_mcu_confg ACR[1] if real speed MBIST (default write "1") ACR 0x18070110[18] 1'b1*/
/*if this bit is 0, HW will do memory auto test under low CPU frequence (26M Hz)*/
/*if this bit is 0, HW will do memory auto test under high CPU frequence(138M Hz) inclulding low CPU frequence*/
CONSYS_REG_WRITE(conn_reg.mcu_base + CONSYS_MCU_CFG_ACR_OFFSET, CONSYS_REG_READ(conn_reg.mcu_base + CONSYS_MCU_CFG_ACR_OFFSET) | CONSYS_MCU_CFG_ACR_MBIST_BIT);
/*"update ANA_WBG(AFE) CR. AFE setting file: MT6752_AFE_SW_patch_REG_xxxx.xlsx" AP Offset = 0x180B2000" AP Offset = 0x180B2000*/
#if 0
/*15.{default no need, Analog HW will inform if this need to be update or not 1 week after IC sample back}
update ANA_WBG(AFE) CR if needed, CONSYS_AFE_REG */
CONSYS_REG_WRITE(CONSYS_AFE_REG_DIG_RCK_01,CONSYS_AFE_REG_DIG_RCK_01_VALUE);
CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_PLL_02,CONSYS_AFE_REG_WBG_PLL_02_VALUE);
CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_WB_TX_01,CONSYS_AFE_REG_WBG_WB_TX_01_VALUE);
#endif
/*16.deassert CONNSYS CPU SW reset (need to check MT6752) 0x10007018 "[12]=1'b0 [31:24]=8'h88 (key)"*/
CONSYS_REG_WRITE(conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET,
(CONSYS_REG_READ(conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET) & ~CONSYS_CPU_SW_RST_BIT) | CONSYS_CPU_SW_RST_CTRL_KEY);
msleep(5);
}else{
#if PWR_ON_OFF_API_AVALIABLE
WMT_PLAT_INFO_FUNC("\n conn_power_off begin\n");
/*power off connsys by API (MT6582, MT6572 are different) API: conn_power_off() */
iRet = conn_power_off();//consult clkmgr owner
WMT_PLAT_INFO_FUNC("\n conn_power_off end\n");
if(iRet)
{
WMT_PLAT_ERR_FUNC("conn_power_off fail(%d)\n",iRet);
}else
{
WMT_PLAT_INFO_FUNC("conn_power_off ok\n");
}
#else
{
INT32 count = 0;
CONSYS_REG_WRITE(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_EN_OFFSET, CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_EN_OFFSET) | CONSYS_PROT_MASK);
//while ((CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_STA1_OFFSET) & CONSYS_PROT_MASK) != CONSYS_PROT_MASK) {
// count++;
// if(count>1000)
// break;
//}
}
/*release connsys ISO, conn_top1_iso_en=1 (MT6572 with the same addr) 0x10006280 [1] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET, CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) | CONSYS_SPM_PWR_ISO_S_BIT);
/*assert SW reset of connsys, conn_ap_sw_rst_b=0 (MT6572 with the same addr) 0x10006280[0] 1'b0 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET, CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) & ~CONSYS_SPM_PWR_RST_BIT);
/*write conn_clk_dis=1, disable connsys clock (MT6572 with the same addr) conn_clk_dis 0x10006280 [4] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET, CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) |CONSYS_CLK_CTRL_BIT);
/*DA_WBG_EN_XBUF=0 */
/*wait 1us */
udelay(1);
/*write conn_top1_mem_PD=1, power off MCU memory (MT6572 with the same addr) 0x10006280 [8] 1'b0 */
//CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET, CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) & ~CONSYS_SRAM_CONN_PD_BIT);
/*write conn_top1_pwr_on=0, power off conn_top1 (MT6572 with the same addr) 0x10006280 [3:2] 2'b00 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET, CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) & ~(CONSYS_SPM_PWR_ON_BIT | CONSYS_SPM_PWR_ON_S_BIT));
#endif
#if CONSYS_PMIC_CTRL_ENABLE
/*set VCN_28 to SW control mode (with PMIC_WRAP API) "1. VCN28_ON_CTRL "0x041C[14] 1'b0*/
//mt6325_upmu_set_rg_vcn28_on_ctrl(0);
/*turn off VCN28 LDO (with PMIC_WRAP API)" 2. RG_VCN28_EN" 0x041C[12]" 1'b0*/
//hwPowerDown(MT6325_POWER_LDO_VCN28, "wcn_drv");
/*AP power off MT6323 VCN_1V8 LDO (with PMIC_WRAP API) RG_VCN18_ON_CTRL "0x0510[1] "1'b0 RG_VCN18_EN" 0x0512[14]" 1'b0"*/
pmic_set_register_value(PMIC_VCN_1V8_ON_CTRL,0);
if(reg_V18){
regulator_disable(reg_V18);
WMT_PLAT_INFO_FUNC("wmt_dev disable VCN_1V8\n");
}
#endif
}
WMT_PLAT_INFO_FUNC("CONSYS-HW-REG-CTRL(0x%08x),finish\n",on);
return 0;
}
