#define CORE_DVFS(_clk_name, _speedo_id, _auto, _mult, _freqs...) \
{ \
.clk_name = _clk_name, \
.speedo_id = _speedo_id, \
.process_id = -1, \
.freqs = {_freqs}, \
.freqs_mult = _mult, \
.millivolts = core_millivolts, \
.auto_dvfs = _auto, \
.dvfs_rail = &tegra3_dvfs_rail_vdd_core, \
}
static struct dvfs core_dvfs_table[] = {
/* Core voltages (mV): 950, 1000, 1050, 1100, 1150, 1200, 1250, 1300, 1350 */
/* Clock limits for internal blocks, PLLs */
CORE_DVFS("cpu_lp", 0, 1, KHZ, 1, 294000, 342000, 427000, 475000, 500000, 500000, 500000, 500000),
#if CONFIG_TEGRA3_LP_CORE_OVERDRIVE
CORE_DVFS("cpu_lp", 1, 1, KHZ, 204000, 295000, 370000, 428000, 475000, 513000, 579000, 620000, 620000),
#else
CORE_DVFS("cpu_lp", 1, 1, KHZ, 204000, 294000, 342000, 427000, 475000, 500000, 500000, 500000, 500000),
#endif
CORE_DVFS("cpu_lp", 2, 1, KHZ, 204000, 295000, 370000, 428000, 475000, 513000, 579000, 620000, 620000),
CORE_DVFS("cpu_lp", 3, 1, KHZ, 1, 1, 1, 1, 1, 1, 450000, 450000, 450000),
CORE_DVFS("emc", 0, 1, KHZ, 1, 266500, 266500, 266500, 266500, 533000, 533000, 533000, 533000),
CORE_DVFS("emc", 1, 1, KHZ, 102000, 408000, 408000, 408000, 408000, 667000, 667000, 667000, 667000),
CORE_DVFS("emc", 2, 1, KHZ, 102000, 450000, 450000, 450000, 450000, 667000, 667000, 800000, 900000),
CORE_DVFS("emc", 3, 1, KHZ, 1, 1, 1, 1, 1, 1, 625000, 625000, 625000),
CORE_DVFS("sbus", 0, 1, KHZ, 1, 136000, 164000, 191000, 216000, 216000, 216000, 216000, 216000),
CORE_DVFS("sbus", 1, 1, KHZ, 102000, 205000, 205000, 227000, 227000, 267000, 267000, 267000, 267000),
#define CORE_DVFS(_clk_name, _speedo_id, _auto, _mult, _freqs...) \
{ \
.clk_name = _clk_name, \
.speedo_id = _speedo_id, \
.process_id = -1, \
.freqs = {_freqs}, \
.freqs_mult = _mult, \
.millivolts = core_millivolts, \
.auto_dvfs = _auto, \
.dvfs_rail = &tegra3_dvfs_rail_vdd_core, \
}
/* For better reading in the DVFS Table */
#define HOST1X ( HUNDSBUAH_MAX_HOST1X_FREQUENCY * 1000 )
static struct dvfs core_dvfs_table[] = {
/* Core voltages (mV): 950, 1000, 1050, 1100, 1150, 1200, 1250, 1300, 1350, 1375, 1410, 1430, HUNDSBUAH_MAX_CORE_VOLTAGE } */
CORE_DVFS("cpu_lp", 2, 1, KHZ, 204000, 295000, 370000, 428000, 475000, 513000, 579000, 620000, 620000, 620000, 620000, 620000, 620000),
CORE_DVFS("emc", 2, 1, KHZ, 102000, 450000, 450000, 450000, 450000, 667000, 667000, 800000, 900000, 900000, 900000, 900000, 900000),
CORE_DVFS("sbus", 2, 1, KHZ, 102000, 205000, 205000, 227000, 227000, 267000, 334000, 334000, 334000, 334000, 334000, 334000, 334000),
CORE_DVFS("vi", 2, 1, KHZ, 1, 219000, 267000, 300000, 371000, 409000, 425000, 425000, 425000, 425000, 425000, 425000, 425000),
CORE_DVFS("vde", 2, 1, KHZ, 200000, 247000, 304000, 352000, 400000, 437000, 484000, 520000, 600000, 650000, 700000, 750000, HUNDSBUAH_MAX_CORE_FREQUENCY * 1000 ),
CORE_DVFS("mpe", 2, 1, KHZ, 200000, 247000, 304000, 361000, 408000, 446000, 484000, 520000, 600000, 650000, 700000, 750000, HUNDSBUAH_MAX_CORE_FREQUENCY * 1000 ),
CORE_DVFS("2d", 2, 1, KHZ, 200000, 267000, 304000, 361000, 408000, 446000, 484000, 520000, 600000, 650000, 700000, 750000, HUNDSBUAH_MAX_CORE_FREQUENCY * 1000 ),
CORE_DVFS("epp", 2, 1, KHZ, 200000, 267000, 304000, 361000, 408000, 446000, 484000, 520000, 600000, 650000, 700000, 750000, HUNDSBUAH_MAX_CORE_FREQUENCY * 1000 ),
CORE_DVFS("3d", 2, 1, KHZ, 200000, 247000, 304000, 361000, 408000, 446000, 484000, 520000, 600000, 650000, 700000, 750000, HUNDSBUAH_MAX_CORE_FREQUENCY * 1000 ),
CORE_DVFS("3d2", 2, 1, KHZ, 200000, 247000, 304000, 361000, 408000, 446000, 484000, 520000, 600000, 650000, 700000, 750000, HUNDSBUAH_MAX_CORE_FREQUENCY * 1000 ),
CORE_DVFS("se", 2, 1, KHZ, 200000, 267000, 304000, 361000, 408000, 446000, 484000, 520000, 600000, 650000, 700000, 750000, HUNDSBUAH_MAX_CORE_FREQUENCY * 1000 ),
CORE_DVFS("host1x", 2, 1, KHZ, 100000, 152000, 188000, 222000, 254000, 267000, 267000, 267000, 300000, 325000, HOST1X, HOST1X, HOST1X),
CORE_DVFS("cbus", 2, 1, KHZ, 200000, 247000, 304000, 352000, 400000, 437000, 484000, 520000, 600000, 650000, 700000, 750000, HUNDSBUAH_MAX_CORE_FREQUENCY * 1000 ),
CORE_DVFS("pll_c", -1, 1, KHZ, 533000, 667000, 667000, 800000, 800000, 1066000, 1066000, 1066000, 1200000, 1300000, 1400000, 1500000, HUNDSBUAH_MAX_CORE_FREQUENCY * 1000 * 2 ),
CORE_DVFS("mipi", 2, 1, KHZ, 1, 1, 1, 1, 1, 60000, 60000, 60000, 60000, 60000, 60000, 60000, 60000),
CORE_DVFS("fuse_burn", -1, 1, KHZ, 1, 1, 1, 1, 26000, 26000, 26000, 26000, 26000, 26000, 26000, 26000, 26000),
CPU_DVFS("cpu", 0, 1, MHZ, 314, 314, 314, 456, 456, 456, 618, 618, 618, 770, 827, 827, 922, 1000),
CPU_DVFS("cpu", 0, 2, MHZ, 494, 494, 494, 675, 675, 817, 817, 922, 922, 1000),
CPU_DVFS("cpu", 0, 3, MHZ, 730, 760, 845, 845, 940, 1000),
CPU_DVFS("cpu", 1, 0, MHZ, 380, 380, 503, 503, 655, 655, 798, 798, 902, 902, 960, 1000, 1200, 1408, 1504, 1600),
CPU_DVFS("cpu", 1, 1, MHZ, 389, 389, 503, 503, 655, 760, 798, 798, 950, 950, 1000, 1200, 1408, 1504, 1600),
CPU_DVFS("cpu", 1, 2, MHZ, 598, 598, 750, 750, 893, 893, 1000, 1200, 1408, 1504, 1600),
CPU_DVFS("cpu", 1, 3, MHZ, 730, 760, 845, 845, 940, 1000, 1200, 1408, 1504, 1600),
CPU_DVFS("cpu", 2, 0, MHZ, 0, 0, 0, 0, 655, 655, 798, 798, 902, 902, 960, 1000, 1100, 1100, 1200),
CPU_DVFS("cpu", 2, 1, MHZ, 0, 0, 0, 0, 655, 760, 798, 798, 950, 950, 1015, 1015, 1100, 1200),
CPU_DVFS("cpu", 2, 2, MHZ, 0, 0, 0, 0, 769, 769, 902, 902, 1026, 1026, 1140, 1140, 1200),
CPU_DVFS("cpu", 2, 3, MHZ, 0, 0, 0, 0, 940, 1000, 1000, 1000, 1130, 1130, 1200),
/* Core voltages (mV): 950, 1000, 1100, 1200, 1225, 1275, 1300 */
CORE_DVFS("emc", -1, 1, KHZ, 57000, 333000, 380000, 666000, 666000, 666000, 760000),
#if 0
/*
* The sdhci core calls the clock ops with a spinlock held, which
* conflicts with the sleeping dvfs api.
* For now, boards must ensure that the core voltage does not drop
* below 1V, or that the sdmmc busses are set to 44 MHz or less.
*/
CORE_DVFS("sdmmc1", -1, 1, KHZ, 44000, 52000, 52000, 52000, 52000, 52000, 52000),
CORE_DVFS("sdmmc2", -1, 1, KHZ, 44000, 52000, 52000, 52000, 52000, 52000, 52000),
CORE_DVFS("sdmmc3", -1, 1, KHZ, 44000, 52000, 52000, 52000, 52000, 52000, 52000),
CORE_DVFS("sdmmc4", -1, 1, KHZ, 44000, 52000, 52000, 52000, 52000, 52000, 52000),
#endif
CORE_DVFS("ndflash", -1, 1, KHZ, 130000, 150000, 158000, 164000, 164000, 164000, 164000),
.freqs = {_freqs}, \
.freqs_mult = _mult, \
.millivolts = core_millivolts, \
.auto_dvfs = _auto, \
.dvfs_rail = &tegra2_dvfs_rail_vdd_core, \
}
static struct dvfs dvfs_init[] = {
/* Cpu voltages (mV): 750, 775, 800, 825, 875, 900, 925, 975, 1000, 1050, 1100 */
CPU_DVFS("cpu", 0, MHZ, 314, 314, 314, 456, 456, 608, 608, 760, 817, 912, 1000),
CPU_DVFS("cpu", 1, MHZ, 314, 314, 314, 456, 456, 618, 618, 770, 827, 922, 1000),
CPU_DVFS("cpu", 2, MHZ, 494, 675, 675, 675, 817, 817, 922, 1000),
CPU_DVFS("cpu", 3, MHZ, 730, 760, 845, 845, 1000),
/* Core voltages (mV): 950, 1000, 1100, 1200, 1275 */
CORE_DVFS("emc", 1, KHZ, 57000, 333000, 333000, 666000, 666000),
#if 0
/*
* The sdhci core calls the clock ops with a spinlock held, which
* conflicts with the sleeping dvfs api.
* For now, boards must ensure that the core voltage does not drop
* below 1V, or that the sdmmc busses are set to 44 MHz or less.
*/
CORE_DVFS("sdmmc1", 1, KHZ, 44000, 52000, 52000, 52000, 52000),
CORE_DVFS("sdmmc2", 1, KHZ, 44000, 52000, 52000, 52000, 52000),
CORE_DVFS("sdmmc3", 1, KHZ, 44000, 52000, 52000, 52000, 52000),
CORE_DVFS("sdmmc4", 1, KHZ, 44000, 52000, 52000, 52000, 52000),
#endif
CORE_DVFS("ndflash", 1, KHZ, 130000, 150000, 158000, 164000, 164000),