Example #1
0
File: str.c Project: lab11/M-ulator
void strb_imm(uint8_t rt, uint8_t rn, uint32_t imm32,
		bool index, bool add, bool wback) {
	DBG2("strb r%02d, [r%02d, #%08x]\n", rt, rn, imm32);

	uint32_t rn_val = CORE_reg_read(rn);
	uint32_t rt_val = CORE_reg_read(rt);

	uint32_t offset_addr;
	if (add) {
		offset_addr = rn_val + imm32;
	} else {
		offset_addr = rn_val - imm32;
	}

	uint32_t address;
	if (index) {
		address = offset_addr;
	} else {
		address = rn_val;
	}

	DBG2("address: %08x\n", address);

	write_byte(address, rt_val & 0xff);

	if (wback) {
		CORE_reg_write(rn, offset_addr);
	}

	DBG2("strb_imm ran\n");
}
Example #2
0
File: str.c Project: lab11/M-ulator
void strb_reg(uint8_t rt, uint8_t rn, uint8_t rm,
		enum SRType shift_t, uint8_t shift_n) {
	union apsr_t apsr = CORE_apsr_read();

	uint32_t offset;
	offset = Shift(CORE_reg_read(rm), 32, shift_t, shift_n, apsr.bits.C);
	uint32_t address;
	address = CORE_reg_read(rn) + offset;

	write_byte(address, CORE_reg_read(rt) & 0xff);
}
Example #3
0
File: str.c Project: lab11/M-ulator
void str_reg(uint8_t rt, uint8_t rn, uint8_t rm,
		enum SRType shift_t, uint8_t shift_n) {
	uint32_t rn_val = CORE_reg_read(rn);
	uint32_t rm_val = CORE_reg_read(rm);
	uint32_t rt_val = CORE_reg_read(rt);

	union apsr_t apsr = CORE_apsr_read();

	uint32_t offset = Shift(rm_val, 32, shift_t, shift_n, apsr.bits.C);
	uint32_t address = rn_val + offset;
	uint32_t data = rt_val;
	write_word_unaligned(address, data);
}
Example #4
0
static void print_reg_state_internal(void) {
	int i;
	union apsr_t apsr = CORE_apsr_read();
	union epsr_t epsr = CORE_epsr_read();

	printf("[Cycle %d]\t\t", cycle);
	printf("\t  T: %d", epsr.bits.T);
	printf("\t  N: %d  Z: %d  C: %d  V: %d  ",
			apsr.bits.N, apsr.bits.Z, apsr.bits.C, apsr.bits.V);
	printf("| ITSTATE: %02x  ", read_itstate());
	printf("\n");
	for (i=0; i<12; ) {
		printf("\tr%02d: %8x\tr%02d: %8x\tr%02d: %8x\tr%02d: %8x\n",
				i, CORE_reg_read(i),
				i+1, CORE_reg_read(i+1),
				i+2, CORE_reg_read(i+2),
				i+3, CORE_reg_read(i+3)
		      );
		i+=4;
	}
	printf("\tr12: %8x\t SP: %8x\t LR: %8x\t PC: %8x\n",
			CORE_reg_read(12),
			CORE_reg_read(SP_REG),
			CORE_reg_read(LR_REG),
			CORE_reg_read(PC_REG)
	      );
}
Example #5
0
File: pop.c Project: lab11/M-ulator
void pop(uint16_t registers) {
	uint32_t address = CORE_reg_read(SP_REG);

	int i;
	for (i = 0; i <= 14; i++) {
		if (registers & (1 << i)) {
			CORE_reg_write(i, read_word(address));
			address += 4;
		}
	}

	if (registers & (1 << 15)) {
		LoadWritePC(read_word(address));
	}

	CORE_reg_write(SP_REG, CORE_reg_read(SP_REG) + 4 * hamming(registers));
}
Example #6
0
void bic_reg(uint8_t rd, uint8_t rn, uint8_t rm,
		bool setflags, enum SRType shift_t, uint8_t shift_n) {
	union apsr_t apsr = CORE_apsr_read();

	uint32_t shifted;
	bool carry_out;
	Shift_C(CORE_reg_read(rm), 32, shift_t, shift_n, apsr.bits.C,
			&shifted, &carry_out);

	uint32_t result = CORE_reg_read(rn) & ~shifted;
	CORE_reg_write(rd, result);

	if (setflags) {
		apsr.bits.N = HIGH_BIT(result);
		apsr.bits.Z = result == 0;
		apsr.bits.C = carry_out;
		CORE_apsr_write(apsr);
	}
}
Example #7
0
void orr_reg(uint8_t setflags, uint8_t rd, uint8_t rn, uint8_t rm,
		enum SRType shift_t, uint8_t shift_n) {
	uint32_t result;
	bool carry_out;

	union apsr_t apsr = CORE_apsr_read();

	Shift_C(CORE_reg_read(rm), 32, shift_t, shift_n, apsr.bits.C, &result, &carry_out);

	result = CORE_reg_read(rn) | result;
	CORE_reg_write(rd, result);

	if (setflags) {
		apsr.bits.N = HIGH_BIT(result);
		apsr.bits.Z = result == 0;
		apsr.bits.C = carry_out;
		CORE_apsr_write(apsr);
	}
}
Example #8
0
void orr_imm(uint8_t rd, uint8_t rn, bool setflags,
		union apsr_t apsr, uint32_t imm32, bool carry) {
	uint32_t result = CORE_reg_read(rn) | imm32;
	CORE_reg_write(rd, result);
	if (setflags) {
		apsr.bits.N = HIGH_BIT(result);
		apsr.bits.Z = result == 0;
		apsr.bits.C = carry;
		CORE_apsr_write(apsr);
	}
}
Example #9
0
void bic_imm(union apsr_t apsr, uint8_t setflags,
		uint8_t rd, uint8_t rn, uint32_t imm32, uint8_t carry) {
	uint32_t result = CORE_reg_read(rn) & (~imm32);
	CORE_reg_write(rd, result);

	if (setflags) {
		apsr.bits.N = HIGH_BIT(result);
		apsr.bits.Z = result == 0;
		apsr.bits.C = carry;
		CORE_apsr_write(apsr);
	}
}
Example #10
0
File: ldm.c Project: inhee/M-ulator
static void ldm(uint8_t rn, uint16_t registers, uint8_t wback) {
	uint32_t address = CORE_reg_read(rn);

	int i;
	for (i = 0; i <= 14; i++) {	// stupid arm inclusive for
		if (registers & (1 << i)) {
			CORE_reg_write(i, read_word(address));
			address += 4;
		}
	}
	if (registers & 0x8000) {
		//LoadWritePC(MemA[address, 4]);
		CORE_ERR_not_implemented("ldm PC");
	}

	if (wback && ((registers & (1 << rn)) == 0)) {
		CORE_reg_write(rn, CORE_reg_read(rn) + 4U*hamming(registers));
	}

	DBG2("ldm had loads of fun\n");
}
Example #11
0
File: str.c Project: lab11/M-ulator
void str_imm(uint8_t rt, uint8_t rn, uint32_t imm32,
		bool index, bool add, bool wback) {
	uint32_t rn_val = CORE_reg_read(rn);

	uint32_t offset_addr;
	if (add)
		offset_addr = rn_val + imm32;
	else
		offset_addr = rn_val - imm32;

	uint32_t address;
	if (index)
		address = offset_addr;
	else
		address = rn_val;

	uint32_t rt_val = CORE_reg_read(rt);
	write_word_unaligned(address, rt_val);

	if (wback)
		CORE_reg_write(rn, offset_addr);
}
Example #12
0
File: str.c Project: lab11/M-ulator
void strd_imm(uint8_t rt, uint8_t rt2, uint8_t rn, uint32_t imm32,
		bool index, bool add, bool wback) {
	uint32_t offset_addr;
	if (add) {
		offset_addr = CORE_reg_read(rn) + imm32;
	} else {
		offset_addr = CORE_reg_read(rn) - imm32;
	}

	uint32_t address;
	if (index) {
		address = offset_addr;
	} else {
		address = CORE_reg_read(rn);
	}

	write_word_aligned(address, CORE_reg_read(rt));
	write_word_aligned(address + 4, CORE_reg_read(rt2));

	if (wback) {
		CORE_reg_write(rn, offset_addr);
	}
}
Example #13
0
void and_imm(union apsr_t apsr, uint8_t setflags, uint8_t rd, uint8_t rn,
		uint32_t imm32, uint8_t carry) {
	uint32_t rn_val = CORE_reg_read(rn);

	uint32_t result = rn_val & imm32;
	if (rd == 15) {
		// ALUWritePC(result);
		CORE_ERR_not_implemented("ALUWritePC and_imm\n");
	} else {
		CORE_reg_write(rd, result);
		if (setflags) {
			apsr.bits.N = HIGH_BIT(result);
			apsr.bits.Z = result == 0;
			apsr.bits.C = carry;
			CORE_apsr_write(apsr);
		}
	}

	DBG2("and_imm done\n");
}