/**
* \brief Enables Cache. The levels/type of Cache to be enabled
* is passed as parameter.
*
* \param enFlag Caches to be enabled.
* 'enFlag' can take one of the below values. \n
* CACHE_ICACHE - To enable Instruction Cache \n
* CACHE_DCACHE - To enable Data/Unified Cache \n
* CACHE_ALL - To enable all levels of Cache
*
* \return None.
*
* \Note Enabling Data Cache enables Unified cache also, if present.
**/
void CacheEnable(unsigned int enFlag)
{
if(enFlag & CACHE_ICACHE)
{
CP15ICacheFlush();
CP15ICacheEnable();
}
if(enFlag & CACHE_DCACHE)
{
/* For Cortex A8, L2EN has to be enabled for L2 Cache */
if(PRIMARY_PART_CORTEX_A8 == CP15MainIdPrimPartNumGet())
{
CP15AuxControlFeatureEnable(CORTEX_A8_L2EN);
}
CP15DCacheFlush();
CP15DCacheEnable();
}
}
/******************************************************************************
** INTERNAL FUNCTION DEFINITIONS
*******************************************************************************/
int main(void)
{
#ifndef _TMS320C6X
unsigned int index;
#endif
/* Setting the Master priority for the VPIF and LCD DMA controllers to highest level */
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_MSTPRI1) &= 0x00FFFFFF;
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_MSTPRI2) &= 0x0FFFFFFF;
#ifdef _TMS320C6X
/* Set MAR bits and configure L1 cache */
CacheEnableMAR((unsigned int)0xC0000000, (unsigned int)0x10000000);
CacheEnable(L1PCFG_L1PMODE_32K | L1DCFG_L1DMODE_32K );
#else
/* Sets up 'Level 1" page table entries.
* The page table entry consists of the base address of the page
* and the attributes for the page. The following operation is to
* setup one-to-one mapping page table for DDR memeory range and set
* the atributes for the same. The DDR memory range is from 0xC0000000
* to 0xCFFFFFFF. Thus the base of the page table ranges from 0xC00 to
* 0xCFF. Cache(C bit) and Write Buffer(B bit) are enabled only for
* those page table entries which maps to DDR RAM and internal RAM.
* All the pages in the DDR range are provided with R/W permissions */
for(index = 0; index < (4*1024); index++)
{
if((index >= 0xC00 && index < 0xD00)|| (index == 0x800))
{
pageTable[index] = (index << 20) | 0x00000C1E;
}
else
{
pageTable[index] = (index << 20) | 0x00000C12;
}
}
/* Configures translation table base register
* with pagetable base address. */
CP15TtbSet((unsigned int )pageTable);
/* Enables MMU */
CP15MMUEnable();
/* Enable Instruction Cache */
CP15ICacheEnable();
/* Enable Data Cache */
CP15DCacheEnable();
#endif
/* Allocate pointers to buffers */
buff_luma[0] = buff_luma1;
buff_luma[1] = buff_luma2;
buff_chroma[0] = buff_chroma1;
buff_chroma[1] = buff_chroma2;
/* Initializing palette for first buffer */
Rgb_buffer1[0] = 0x4000;
for (i = 1; i < 16; i++)
Rgb_buffer1[i] = 0x0000;
videoTopRgb1 = Rgb_buffer1 + i;
/* Initializing palette for second buffer */
Rgb_buffer2[0] = 0x4000;
for (i = 1; i < 16; i++)
Rgb_buffer2[i] = 0x0000;
videoTopRgb2 = Rgb_buffer2 + i;
/* Power on VPIF */
PSCModuleControl(SOC_PSC_1_REGS, HW_PSC_VPIF, PSC_POWERDOMAIN_ALWAYS_ON,
PSC_MDCTL_NEXT_ENABLE);
/* Initializing ARM/DSP INTC */
SetupIntc();
/* Initialize I2C and program UI GPIO expander, TVP5147, and ADV7343 via I2C */
I2CPinMuxSetup(0);
/* enable video via gpio expander to ensure we have exclusive access to the bus */
I2CCodecIfInit(SOC_I2C_0_REGS, INT_CHANNEL_I2C, I2C_SLAVE_UI_EXPANDER);
I2CGPIOInit(SOC_I2C_0_REGS);
I2CGPIOSetOutput(SOC_I2C_0_REGS);
/*Initialize the TVP5147 to accept composite video */
I2CCodecIfInit(SOC_I2C_0_REGS, INT_CHANNEL_I2C,
I2C_SLAVE_CODEC_TVP5147_2_COMPOSITE);
TVP5147CompositeInit(SOC_I2C_0_REGS);
/* Setup VPIF pinmux */
VPIFPinMuxSetup();
/* Setup LCD */
SetUpLCD();
/* Initialize VPIF */
SetUpVPIFRx();
VPIFDMARequestSizeConfig(SOC_VPIF_0_REGS, VPIF_REQSIZE_ONE_TWENTY_EIGHT);
VPIFEmulationControlSet(SOC_VPIF_0_REGS, VPIF_HALT);
/* Initialize buffer addresses for 1st frame*/
VPIFCaptureFBConfig(SOC_VPIF_0_REGS, VPIF_CHANNEL_0, VPIF_TOP_FIELD,
VPIF_LUMA, (unsigned int) buff_luma[0], CAPTURE_IMAGE_WIDTH*2);
VPIFCaptureFBConfig(SOC_VPIF_0_REGS, VPIF_CHANNEL_0, VPIF_TOP_FIELD,
VPIF_CHROMA, (unsigned int) buff_chroma[0], CAPTURE_IMAGE_WIDTH*2);
VPIFCaptureFBConfig(SOC_VPIF_0_REGS, VPIF_CHANNEL_0, VPIF_BOTTOM_FIELD,
VPIF_LUMA, (unsigned int) (buff_luma[0] + CAPTURE_IMAGE_WIDTH), CAPTURE_IMAGE_WIDTH*2);
VPIFCaptureFBConfig(SOC_VPIF_0_REGS, VPIF_CHANNEL_0, VPIF_BOTTOM_FIELD,
VPIF_CHROMA, (unsigned int) (buff_chroma[0] + CAPTURE_IMAGE_WIDTH), CAPTURE_IMAGE_WIDTH*2);
/* configuring the base ceiling */
RasterDMAFBConfig(SOC_LCDC_0_REGS, (unsigned int) Rgb_buffer2,
(unsigned int) (Rgb_buffer2 + DISPLAY_IMAGE_WIDTH * DISPLAY_IMAGE_HEIGHT + 15), 0);
RasterDMAFBConfig(SOC_LCDC_0_REGS, (unsigned int) Rgb_buffer2,
(unsigned int) (Rgb_buffer2 + DISPLAY_IMAGE_WIDTH * DISPLAY_IMAGE_HEIGHT + 15), 1);
/* Enable capture */
VPIFCaptureChanenEnable(SOC_VPIF_0_REGS, VPIF_CHANNEL_0);
/* Enable VPIF interrupt */
VPIFInterruptEnable(SOC_VPIF_0_REGS, VPIF_FRAMEINT_CH0);
VPIFInterruptEnableSet(SOC_VPIF_0_REGS, VPIF_FRAMEINT_CH0);
/* enable End of frame interrupt */
RasterEndOfFrameIntEnable(SOC_LCDC_0_REGS);
/* enable raster */
RasterEnable(SOC_LCDC_0_REGS);
buffcount++;
buffcount2 = buffcount - 1;
/* Run forever */
while (1)
{
/* Wait here till a new frame is not captured */
while (!captured);
/* Process the next buffer only when both the raster buffers
* are pointing to the current buffer to avoid jitter effect */
if (updated == 3)
{
processed = 0;
changed = 0;
updated = 0;
/* Convert the buffer from CBCR422 semi-planar to RGB565,
* Flush and invalidate the processed buffer so that the DMA reads the processed data,
* set the flag for the buffer to be displayed on the LCD (which would be the processed buffer)
* and notify the LCD of availability of a processed buffer.
* The output buffers are ping-ponged each time. */
if (pingpong)
{
cbcr422sp_to_rgb565_c(
(const unsigned char *) (videoTopC + OFFSET),
DISPLAY_IMAGE_HEIGHT, CAPTURE_IMAGE_WIDTH, ccCoeff,
(const unsigned char *) (videoTopY + OFFSET),
CAPTURE_IMAGE_WIDTH, videoTopRgb1, DISPLAY_IMAGE_WIDTH, DISPLAY_IMAGE_WIDTH);
#ifdef _TMS320C6X
CacheWBInv((unsigned int) videoTopRgb1, DISPLAY_IMAGE_WIDTH * DISPLAY_IMAGE_HEIGHT * 2);
#else
CP15DCacheCleanBuff((unsigned int) videoTopRgb1,DISPLAY_IMAGE_WIDTH * DISPLAY_IMAGE_HEIGHT * 2);
#endif
display_buff_1 = 1;
changed = 1;
}
else
{
cbcr422sp_to_rgb565_c(
(const unsigned char *) (videoTopC + OFFSET),
DISPLAY_IMAGE_HEIGHT, CAPTURE_IMAGE_WIDTH, ccCoeff,
(const unsigned char *) (videoTopY + OFFSET),
CAPTURE_IMAGE_WIDTH, videoTopRgb2, DISPLAY_IMAGE_WIDTH, DISPLAY_IMAGE_WIDTH);
#ifdef _TMS320C6X
CacheWBInv((unsigned int) videoTopRgb2, DISPLAY_IMAGE_WIDTH * DISPLAY_IMAGE_HEIGHT * 2);
#else
CP15DCacheCleanBuff((unsigned int) videoTopRgb2, DISPLAY_IMAGE_WIDTH * DISPLAY_IMAGE_HEIGHT * 2);
#endif
display_buff_1 = 0;
changed = 1;
}
pingpong = !pingpong;
captured = 0;
processed = 1;
}
}
}
//*****************************************************************************
//
// The main code for the application. It sets up the peripherals, displays the
// splash screens, and then manages the interaction between the game and the
// screen saver.
//
//*****************************************************************************
int
main(void)
{
tRectangle sRect;
#ifndef _TMS320C6X
unsigned int index;
#endif
SetupIntc();
/* Configuring UART2 instance for serial communication. */
UARTStdioInit();
#ifdef _TMS320C6X
CacheEnableMAR((unsigned int)0xC0000000, (unsigned int)0x20000000);
CacheEnable(L1PCFG_L1PMODE_32K | L1DCFG_L1DMODE_32K | L2CFG_L2MODE_256K);
#else
/* Sets up 'Level 1" page table entries.
* The page table entry consists of the base address of the page
* and the attributes for the page. The following operation is to
* setup one-to-one mapping page table for DDR memeory range and set
* the atributes for the same. The DDR memory range is from 0xC0000000
* to 0xDFFFFFFF. Thus the base of the page table ranges from 0xC00 to
* 0xDFF. Cache(C bit) and Write Buffer(B bit) are enabled only for
* those page table entries which maps to DDR RAM and internal RAM.
* All the pages in the DDR range are provided with R/W permissions
*/
for(index = 0; index < (4*1024); index++)
{
if((index >= 0xC00 && index < 0xE00)|| (index == 0x800))
{
pageTable[index] = (index << 20) | 0x00000C1E;
}
else
{
pageTable[index] = (index << 20) | 0x00000C12;
}
}
/* Configures translation table base register
* with pagetable base address.
*/
CP15TtbSet((unsigned int )pageTable);
/* Enables MMU */
CP15MMUEnable();
/* Enable Instruction Cache */
CP15ICacheEnable();
/* Enable Data Cache */
CP15DCacheEnable();
#endif
SetUpLCD();
ConfigureFrameBuffer();
GrOffScreen16BPPInit(&g_sSHARP480x272x16Display0, (unsigned char *)g_pucBuffer0, LCD_WIDTH, LCD_HEIGHT);
GrOffScreen16BPPInit(&g_sSHARP480x272x16Display1, (unsigned char *)g_pucBuffer1, LCD_WIDTH, LCD_HEIGHT);
// Initialize a drawing context.
GrContextInit(&sContext0, &g_sSHARP480x272x16Display0);
GrContextInit(&sContext1, &g_sSHARP480x272x16Display1);
/* enable End of frame interrupt */
RasterEndOfFrameIntEnable(SOC_LCDC_0_REGS);
/* enable raster */
RasterEnable(SOC_LCDC_0_REGS);
PeripheralsSetup();
I2C0IntRegister(4);
AIC31Init();
ToneLoopInit();
/* Start playing the tone */
ToneLoopStart();
// TS init
TouchInit();
GrContextForegroundSet(&sContext0, ClrBlack);
GrContextForegroundSet(&sContext1, ClrBlack);
sRect.sXMin = GAME_X - 1;
sRect.sYMin = GAME_Y - 1;
sRect.sXMax = GAME_X + GAME_W;
sRect.sYMax = GAME_Y + GAME_H;
GrRectFill(&sContext0, &sRect);
GrRectFill(&sContext1, &sRect);
GrImageDraw(&sContext0, g_pucTILogo128x96, GAME_X, GAME_Y);
GrImageDraw(&sContext1, g_pucTILogo128x96, GAME_X, GAME_Y);
Delay(0x5FFFFF);
// Confiure and start timer2
Timer2Config();
Timer2Start();
// Loop forever.
while(1)
{
// Display the main screen.
if(MainScreen())
{
// The button was pressed, so start the game.
PlayGame();
}
else
{
// The button was not pressed during the timeout period, so start
// the screen saver.
ScreenSaver();
}
}
}
/*
** Main function. The application starts here.
*/
int main(void)
{
unsigned int index;
unsigned int j;
int result = 0;
/*
** Sets up Section page tables. This is only first level
** page table, each page is of size 1MB
*/
for(index = 0; index < (4*1024); index++)
{
/* Set the cacheable memory attributes */
if((index >= 0x800 && index < 0x880) || (index == 0x403))
{
pageTable[index] = (index << 20) | CACHEABLE_TLB_ATTR;
}
/* Set the non-cacheable memory attributes */
else
{
pageTable[index] = (index << 20) | NORM_TLB_ATTR;
}
}
/* Invalidate the TLB, pipeline */
CP15TlbInvalidate();
CP15BranchPredictorInvalidate();
CP15BranchPredictionEnable();
CP15DomainAccessClientSet();
/* Set TTB0 value. We use only TTB0 here (N = 0) */
CP15Ttb0Set(((unsigned int )pageTable) | RGN_L2_WBWA);
/* Enables MMU */
CP15MMUEnable();
/* Flush and enable Instruction Cache */
CP15ICacheFlush();
CP15ICacheEnable();
PeripheralsSetUp();
/* Initialize the ARM Interrupt Controller */
IntAINTCInit();
/* Register the ISRs */
Timer2IntRegister();
Timer4IntRegister();
EnetIntRegister();
RtcIntRegister();
HSMMCSDIntRegister();
IntRegister(127, dummyIsr);
IntMasterIRQEnable();
/* Enable system interrupts */
IntSystemEnable(SYS_INT_RTCINT);
IntPrioritySet(SYS_INT_RTCINT, 0, AINTC_HOSTINT_ROUTE_IRQ);
IntSystemEnable(SYS_INT_3PGSWTXINT0);
IntPrioritySet(SYS_INT_3PGSWTXINT0, 0, AINTC_HOSTINT_ROUTE_IRQ);
IntSystemEnable(SYS_INT_3PGSWRXINT0);
IntPrioritySet(SYS_INT_3PGSWRXINT0, 0, AINTC_HOSTINT_ROUTE_IRQ);
IntSystemEnable(SYS_INT_TINT2);
IntPrioritySet(SYS_INT_TINT2, 0, AINTC_HOSTINT_ROUTE_IRQ);
IntSystemEnable(SYS_INT_TINT4);
IntPrioritySet(SYS_INT_TINT4, 0, AINTC_HOSTINT_ROUTE_IRQ);
IntSystemEnable(SYS_INT_MMCSD0INT);
IntPrioritySet(SYS_INT_MMCSD0INT, 0, AINTC_HOSTINT_ROUTE_IRQ);
IntSystemEnable(SYS_INT_EDMACOMPINT);
IntPrioritySet(SYS_INT_EDMACOMPINT, 0, AINTC_HOSTINT_ROUTE_IRQ);
IntSystemEnable(127);
IntPrioritySet(127, 0, AINTC_HOSTINT_ROUTE_IRQ);
RtcInit();
UARTStdioInit();
HSMMCSDContolInit();
DelayTimerSetup();
Timer2Config();
Timer4Config();
LedIfConfig();
Timer2IntEnable();
Timer4IntEnable();
RtcSecIntEnable();
InitI2C();
Timer4Start();
// Read config from files
HSMMCSDCardAccessSetup();
configRead();
LedOn( USER_LED_1 );
for( j = 0; j < 1000000; ++j );
LedOff( USER_LED_1 );
LedOn( USER_LED_2 );
for( j = 0; j < 1000000; ++j );
LedOff( USER_LED_2 );
LedOn( USER_LED_3 );
for( j = 0; j < 1000000; ++j );
LedOff( USER_LED_3 );
LedOn( USER_LED_4 );
for( j = 0; j < 1000000; ++j );
LedOff( USER_LED_4 );
// TEMP
//i2cTest();
/*
** Loop for ever. Necessary actions shall be taken
** after detecting the click.
*/
while( 1 )
{
EnetStatusCheckNUpdate();
if( runCommand )
{
// Command blink
LedOn( USER_LED_1 );
if( runData[ runIndex + 1 ] == 'D' )
{
if( runData[ runIndex + 2 ] == 'S' )
{
UARTPuts( "** DAC SET\n\r", -1 );
if( runData[ runIndex + 3 ] == 'A' )
{
i2cDAC_Set( 0,
runData[ runIndex + 4 ], runData[ runIndex + 5 ] );
}
if( runData[ runIndex + 6 ] == 'B' )
{
i2cDAC_Set( 1,
runData[ runIndex + 7 ], runData[ runIndex + 8 ] );
}
if( runData[ runIndex + 9 ] == 'C' )
{
i2cDAC_Set( 2,
runData[ runIndex + 10 ], runData[ runIndex + 11 ] );
}
if( runData[ runIndex + 12 ] == 'D' )
{
i2cDAC_Set( 3,
runData[ runIndex + 13 ], runData[ runIndex + 14 ] );
}
}
else if( runData[ runIndex + 2 ] == 'G' )
{
UARTPuts( "** DAC GET\n\r", -1 );
uartData[ 0 ] = 15;
uartData[ 1 ] = 'D';
uartData[ 2 ] = 'G';
uartData[ 3 ] = 'A';
i2cDAC_Get( 0, &uartData[ 4 ] );
uartData[ 6 ] = 'B';
i2cDAC_Get( 1, &uartData[ 7 ] );
uartData[ 9 ] = 'C';
i2cDAC_Get( 2, &uartData[ 10 ] );
uartData[ 12 ] = 'D';
i2cDAC_Get( 3, &uartData[ 13 ] );
net_ext_send( uartData, 15 );
}
}
else if( runData[ runIndex + 1 ] == 'G' )
{
if( runData[ runIndex + 2 ] == 'S' )
{
if( runData[ runIndex + 3 ] == 0 ) // Off
{
UARTPuts( "** GPIO OFF\n\r", -1 );
i2cGPIO_Off( 0, 1 << runData[ runIndex + 4 ] );
}
else if( runData[ runIndex + 3 ] == 1 ) // On
{
UARTPuts( "** GPIO ON\n\r", -1 );
i2cGPIO_On( 0, 1 << runData[ runIndex + 4 ] );
}
}
else if( runData[ runIndex + 2 ] == 'G' )
{
UARTPuts( "** GPIO GET\n\r", -1 );
uartData[ 0 ] = 5;
uartData[ 1 ] = 'G';
uartData[ 2 ] = 'G';
i2cGPIO_Get( &uartData[ 3 ] );
net_ext_send( uartData, 5 );
}
}
else if( runData[ runIndex + 1 ] == 'U' )
{
UARTPuts( "** UART\n\r", -1 );
i2cUART_Send( &(runData[ runIndex + 2 ]), 6 );
}
runCommand -= runData[ runIndex + 0 ];
if( runCommand > 0 )
{
runIndex += runData[ runIndex + 0 ];
}
else
{
runIndex = 0;
}
LedOff( USER_LED_1 );
}
result = i2cUART_Recv( &( uartData[ 2 ] ), 30 );
if( result > 0 )
{
UARTPuts( "** UART Recv: ", -1 );
for( index = 0; index < result; ++index )
{
UARTPutHexNum( uartData[ index + 2 ] );
UARTPutc( ' ' );
}
UARTPutc( '\n' );
UARTPutc( '\r' );
// Return the stage position info to the GUI
if( uartData[ 3 ] == 0x0A ||
uartData[ 3 ] == 0x3C )
{
uartData[ 0 ] = result + 2;
uartData[ 1 ] = 'U';
net_ext_send( uartData, result + 2 );
}
}
}
}
