#define PARENT(P) (((CLK_ID_##P)<<16) | CLK_FLG_PARENT)
#define DEF_CLK(N,FLAG) \
[CLK_ID_##N] = { .name = CLK_NAME_##N, .flags = FLAG, }
[CLK_ID_EXT] = {.name = "noclk", 1},
DEF_CLK(EXT0, 0),
DEF_CLK(EXT1, 0),
DEF_CLK(OTGPHY, 0),
[CLK_ID_PLL] = {.name = "noclk", 1},
DEF_CLK(APLL, PLL(0)),
DEF_CLK(MPLL, PLL(0)),
DEF_CLK(SCLKA, PARENT(APLL)),
[CLK_ID_CPPCR] = {.name = "noclk", 1},
DEF_CLK(CCLK, CPCCR(0)),
DEF_CLK(L2CLK, CPCCR(0)),
DEF_CLK(H0CLK, CPCCR(H0DIV)),
DEF_CLK(H2CLK, CPCCR(H2DIV)),
DEF_CLK(PCLK, CPCCR(PDIV)),
[CLK_ID_DEVICES] = {.name = "noclk", 1},
DEF_CLK(EFUSE, GATE(1) | PARENT(H2CLK)),
DEF_CLK(OTG, GATE(3)),
DEF_CLK(MSC0, GATE(4) | PARENT(CGU_MSC_MUX)),
DEF_CLK(MSC1, GATE(5) | PARENT(CGU_MSC_MUX)),
DEF_CLK(SSI0, GATE(6) | PARENT(CGU_SSI)),
DEF_CLK(I2C0, GATE(7) | PARENT(PCLK)),
DEF_CLK(I2C1, GATE(8) | PARENT(PCLK)),
DEF_CLK(AIC, GATE(11) | PARENT(CGU_I2S)),
#define CGU_AUDIO(no) (((no)<<24) | CLK_FLG_CGU_AUDIO)
#define TCU_WDT(no) (((no)<<24) | CLK_FLG_WDT)
#define PLL(no) (((no)<<24) | CLK_FLG_PLL)
#define PARENT(P) (((CLK_ID_##P)<<16) | CLK_FLG_PARENT)
#define RELATIVE(P) (((CLK_ID_##P)<<16) | CLK_FLG_RELATIVE)
#define DEF_CLK(N,FLAG) \
[CLK_ID_##N] = { .name = CLK_NAME_##N, .flags = FLAG, }
DEF_CLK(EXT0, CLK_FLG_NOALLOC),
DEF_CLK(EXT1, CLK_FLG_NOALLOC),
DEF_CLK(OTGPHY, CLK_FLG_NOALLOC),
DEF_CLK(APLL, PLL(CPM_CPAPCR)),
DEF_CLK(MPLL, PLL(CPM_CPMPCR)),
DEF_CLK(SCLKA, CPCCR(SCLKA)),
DEF_CLK(CCLK, CPCCR(CDIV)),
DEF_CLK(L2CLK, CPCCR(L2CDIV)),
DEF_CLK(H0CLK, CPCCR(H0DIV)),
DEF_CLK(H2CLK, CPCCR(H2DIV)),
DEF_CLK(PCLK, CPCCR(PDIV)),
DEF_CLK(NEMC, GATE(0) | PARENT(H2CLK)),
DEF_CLK(EFUSE, GATE(1) | PARENT(H2CLK)),
DEF_CLK(SFC, GATE(2) | PARENT(CGU_SFC)),
DEF_CLK(OTG, GATE(3)),
DEF_CLK(MSC0, GATE(4) | PARENT(PCLK)),
DEF_CLK(MSC1, GATE(5) | PARENT(PCLK)),
DEF_CLK(SCC, GATE(6) | PARENT(PCLK)),
DEF_CLK(I2C0, GATE(7) | PARENT(PCLK)),
DEF_CLK(I2C1, GATE(8) | PARENT(PCLK)),
