/* Set the boot bank to the alternate bank */
void cpld_set_altbank(void)
{
u8 reg4 = CPLD_READ(soft_mux_on);
u8 reg7 = CPLD_READ(vbank);
CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL);
reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK;
CPLD_WRITE(vbank, reg7);
CPLD_WRITE(system_rst, 1);
}
int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int rc = 0;
unsigned int i;
if (argc <= 1)
return cmd_usage(cmdtp);
if (strcmp(argv[1], "reset") == 0) {
if (strcmp(argv[2], "altbank") == 0)
cpld_set_altbank();
else
cpld_clear_altbank();
cpld_reset();
} else if (strcmp(argv[1], "watchdog") == 0) {
static char *period[8] = {"1ms", "10ms", "30ms", "disable",
"100ms", "1s", "10s", "60s"};
for (i = 0; i < ARRAY_SIZE(period); i++) {
if (strcmp(argv[2], period[i]) == 0)
CPLD_WRITE(wd_cfg, i);
}
} else if (strcmp(argv[1], "lane_mux") == 0) {
u32 lane = simple_strtoul(argv[2], NULL, 16);
u8 val = (u8)simple_strtoul(argv[3], NULL, 16);
u8 reg = CPLD_READ(serdes_mux);
switch (lane) {
case 0x6:
reg &= ~SERDES_MUX_LANE_6_MASK;
reg |= val << SERDES_MUX_LANE_6_SHIFT;
break;
case 0xa:
reg &= ~SERDES_MUX_LANE_A_MASK;
reg |= val << SERDES_MUX_LANE_A_SHIFT;
break;
case 0xc:
reg &= ~SERDES_MUX_LANE_C_MASK;
reg |= val << SERDES_MUX_LANE_C_SHIFT;
break;
case 0xd:
reg &= ~SERDES_MUX_LANE_D_MASK;
reg |= val << SERDES_MUX_LANE_D_SHIFT;
break;
default:
printf("Invalid value\n");
break;
}
CPLD_WRITE(serdes_mux, reg);
#ifdef DEBUG
} else if (strcmp(argv[1], "dump") == 0) {
cpld_dump_regs();
#endif
} else
rc = cmd_usage(cmdtp);
return rc;
}
/**
* Set the boot bank to the alternate bank
*/
void __cpld_set_altbank(void)
{
u8 reg5 = CPLD_READ(sw_ctl_on);
CPLD_WRITE(sw_ctl_on, reg5 | CPLD_SWITCH_BANK_ENABLE);
CPLD_WRITE(fbank_sel, 1);
CPLD_WRITE(system_rst, 1);
}
int checkboard(void)
{
static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
u8 cfg_rcw_src1, cfg_rcw_src2;
u16 cfg_rcw_src;
u8 sd1refclk_sel;
puts("Board: LS1046ARDB, boot from ");
cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
cpld_rev_bit(&cfg_rcw_src1);
cfg_rcw_src = cfg_rcw_src1;
cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
if (cfg_rcw_src == 0x44)
printf("QSPI vBank %d\n", CPLD_READ(vbank));
else if (cfg_rcw_src == 0x40)
puts("SD\n");
else
puts("Invalid setting of SW5\n");
printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver),
CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
puts("SERDES Reference Clocks:\n");
sd1refclk_sel = CPLD_READ(sd1refclk_sel);
printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
return 0;
}
/*
* Initialize the lane_to_slot[] array.
*
* On the P2040RDB board the mapping is controlled by CPLD register.
*/
static void initialize_lane_to_slot(void)
{
u8 mux = CPLD_READ(serdes_mux);
lane_to_slot[6] = (mux & SERDES_MUX_LANE_6_MASK) ? 0 : 1;
lane_to_slot[10] = (mux & SERDES_MUX_LANE_A_MASK) ? 0 : 2;
lane_to_slot[12] = (mux & SERDES_MUX_LANE_C_MASK) ? 0 : 2;
lane_to_slot[13] = (mux & SERDES_MUX_LANE_D_MASK) ? 0 : 2;
}
int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int rc = 0;
if (argc <= 1)
return cmd_usage(cmdtp);
if (strcmp(argv[1], "reset") == 0) {
if (strcmp(argv[2], "altbank") == 0)
cpld_set_altbank();
else
cpld_set_defbank();
} else if (strcmp(argv[1], "lane_mux") == 0) {
u32 lane = simple_strtoul(argv[2], NULL, 16);
u8 val = (u8)simple_strtoul(argv[3], NULL, 16);
u8 reg = CPLD_READ(serdes_mux);
switch (lane) {
case 0x6:
reg &= ~SERDES_MUX_LANE_6_MASK;
reg |= val << SERDES_MUX_LANE_6_SHIFT;
break;
case 0xa:
reg &= ~SERDES_MUX_LANE_A_MASK;
reg |= val << SERDES_MUX_LANE_A_SHIFT;
break;
case 0xc:
reg &= ~SERDES_MUX_LANE_C_MASK;
reg |= val << SERDES_MUX_LANE_C_SHIFT;
break;
case 0xd:
reg &= ~SERDES_MUX_LANE_D_MASK;
reg |= val << SERDES_MUX_LANE_D_SHIFT;
break;
default:
printf("Invalid value\n");
break;
}
CPLD_WRITE(serdes_mux, reg);
#ifdef DEBUG
} else if (strcmp(argv[1], "dump") == 0) {
cpld_dump_regs();
#endif
} else
rc = cmd_usage(cmdtp);
return rc;
}
u_int8_t
zflash_reg8_read(void *arg, int reg)
{
struct zflash_softc *sc = arg;
u_int8_t value;
switch (reg) {
case FLASH_REG_DATA:
value = CPLD_READ(sc, CPLD_REG_FLASHIO);
break;
case FLASH_REG_READY:
value = (CPLD_READ(sc, CPLD_REG_FLASHCTL) &
FLASHCTL_RYBY) != 0;
break;
default:
#ifdef DIAGNOSTIC
printf("%s: read from pseudo-register %02x\n",
sc->sc_flash.sc_dev.dv_xname, reg);
#endif
value = 0;
break;
}
return value;
}
int checkboard(void)
{
static const char *freq[3] = {"100.00MHZ", "156.25MHZ"};
#ifndef CONFIG_SD_BOOT
u8 cfg_rcw_src1, cfg_rcw_src2;
u32 cfg_rcw_src;
#endif
u32 sd1refclk_sel;
printf("Board: LS1043ARDB, boot from ");
#ifdef CONFIG_SD_BOOT
puts("SD\n");
#else
cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
cpld_rev_bit(&cfg_rcw_src1);
cfg_rcw_src = cfg_rcw_src1;
cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
if (cfg_rcw_src == 0x25)
printf("vBank %d\n", CPLD_READ(vbank));
else if (cfg_rcw_src == 0x106)
puts("NAND\n");
else
printf("Invalid setting of SW4\n");
#endif
printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver),
CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
puts("SERDES Reference Clocks:\n");
sd1refclk_sel = CPLD_READ(sd1refclk_sel);
printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
return 0;
}
void cpld_write(unsigned int reg, u8 value)
{
void *p = (void *)CONFIG_SYS_CPLD_BASE;
out_8(p + reg, value);
}
/**
* Set the boot bank to the alternate bank
*/
void cpld_set_altbank(void)
{
u8 val, curbank, altbank, override;
val = CPLD_READ(vbank);
curbank = val & CPLD_BANK_SEL_MASK;
switch (curbank) {
case CPLD_SELECT_BANK0:
case CPLD_SELECT_BANK4:
altbank = CPLD_SELECT_BANK4;
CPLD_WRITE(vbank, altbank);
override = CPLD_READ(software_on);
CPLD_WRITE(software_on, override | CPLD_BANK_SEL_EN);
CPLD_WRITE(sys_reset, CPLD_SYSTEM_RESET);
break;
default:
printf("CPLD Altbank Fail: Invalid value!\n");
return;
}
static void cpld_dump_regs(void)
{
printf("cpld_ver = %x\n", CPLD_READ(cpld_ver));
printf("cpld_ver_sub = %x\n", CPLD_READ(cpld_ver_sub));
printf("pcba_ver = %x\n", CPLD_READ(pcba_ver));
printf("soft_mux_on = %x\n", CPLD_READ(soft_mux_on));
printf("cfg_rcw_src1 = %x\n", CPLD_READ(cfg_rcw_src1));
printf("cfg_rcw_src2 = %x\n", CPLD_READ(cfg_rcw_src2));
printf("vbank = %x\n", CPLD_READ(vbank));
printf("sysclk_sel = %x\n", CPLD_READ(sysclk_sel));
printf("uart_sel = %x\n", CPLD_READ(uart_sel));
printf("sd1refclk_sel = %x\n", CPLD_READ(sd1refclk_sel));
printf("tdmclk_mux_sel = %x\n", CPLD_READ(tdmclk_mux_sel));
printf("sdhc_spics_sel = %x\n", CPLD_READ(sdhc_spics_sel));
printf("status_led = %x\n", CPLD_READ(status_led));
putc('\n');
}
static void cpld_dump_regs(void)
{
printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver));
printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub));
printf("pcba_ver = 0x%02x\n", CPLD_READ(pcba_ver));
printf("system_rst = 0x%02x\n", CPLD_READ(system_rst));
printf("sw_ctl_on = 0x%02x\n", CPLD_READ(sw_ctl_on));
printf("por_cfg = 0x%02x\n", CPLD_READ(por_cfg));
printf("switch_strobe = 0x%02x\n", CPLD_READ(switch_strobe));
printf("jtag_sel = 0x%02x\n", CPLD_READ(jtag_sel));
printf("sdbank1_clk = 0x%02x\n", CPLD_READ(sdbank1_clk));
printf("sdbank2_clk = 0x%02x\n", CPLD_READ(sdbank2_clk));
printf("fbank_sel = 0x%02x\n", CPLD_READ(fbank_sel));
printf("serdes_mux = 0x%02x\n", CPLD_READ(serdes_mux));
printf("SW[2] = 0x%02x\n", in_8(&CPLD_SW(2)));
putc('\n');
}
int
zflash_regx_write_page(void *arg, caddr_t data, caddr_t oob)
{
struct zflash_softc *sc = arg;
int i;
if (oob == NULL || sc->sc_flash.sc_flashdev->pagesize != 512) {
flash_reg8_write_page(&sc->sc_flash, data, oob);
return 0;
}
if (oob[OOB_JFFS2_ECC0] != 0xff || oob[OOB_JFFS2_ECC1] != 0xff ||
oob[OOB_JFFS2_ECC2] != 0xff || oob[OOB_JFFS2_ECC3] != 0xff ||
oob[OOB_JFFS2_ECC4] != 0xff || oob[OOB_JFFS2_ECC5] != 0xff) {
#ifdef DIAGNOSTIC
printf("%s: non-FF ECC bytes in OOB data\n",
sc->sc_flash.sc_dev.dv_xname);
#endif
return EINVAL;
}
CPLD_WRITE(sc, CPLD_REG_ECCCLRR, 0x00);
for (i = 0; i < sc->sc_flash.sc_flashdev->pagesize / 2; i++)
flash_reg8_write(&sc->sc_flash, FLASH_REG_DATA, data[i]);
oob[OOB_JFFS2_ECC0] = ~CPLD_READ(sc, CPLD_REG_ECCLPUB);
oob[OOB_JFFS2_ECC1] = ~CPLD_READ(sc, CPLD_REG_ECCLPLB);
oob[OOB_JFFS2_ECC2] = (~CPLD_READ(sc, CPLD_REG_ECCCP) << 2) | 0x03;
if (CPLD_READ(sc, CPLD_REG_ECCCNTR) != 0) {
printf("%s: ECC failed\n", sc->sc_flash.sc_dev.dv_xname);
oob[OOB_JFFS2_ECC0] = 0xff;
oob[OOB_JFFS2_ECC1] = 0xff;
oob[OOB_JFFS2_ECC2] = 0xff;
return EIO;
}
CPLD_WRITE(sc, CPLD_REG_ECCCLRR, 0x00);
for (; i < sc->sc_flash.sc_flashdev->pagesize; i++)
flash_reg8_write(&sc->sc_flash, FLASH_REG_DATA, data[i]);
oob[OOB_JFFS2_ECC3] = ~CPLD_READ(sc, CPLD_REG_ECCLPUB);
oob[OOB_JFFS2_ECC4] = ~CPLD_READ(sc, CPLD_REG_ECCLPLB);
oob[OOB_JFFS2_ECC5] = (~CPLD_READ(sc, CPLD_REG_ECCCP) << 2) | 0x03;
if (CPLD_READ(sc, CPLD_REG_ECCCNTR) != 0) {
printf("%s: ECC failed\n", sc->sc_flash.sc_dev.dv_xname);
oob[OOB_JFFS2_ECC0] = 0xff;
oob[OOB_JFFS2_ECC1] = 0xff;
oob[OOB_JFFS2_ECC2] = 0xff;
oob[OOB_JFFS2_ECC3] = 0xff;
oob[OOB_JFFS2_ECC4] = 0xff;
oob[OOB_JFFS2_ECC5] = 0xff;
return EIO;
}
for (i = 0; i < sc->sc_flash.sc_flashdev->oobsize; i++)
flash_reg8_write(&sc->sc_flash, FLASH_REG_DATA, oob[i]);
oob[OOB_JFFS2_ECC0] = 0xff;
oob[OOB_JFFS2_ECC1] = 0xff;
oob[OOB_JFFS2_ECC2] = 0xff;
oob[OOB_JFFS2_ECC3] = 0xff;
oob[OOB_JFFS2_ECC4] = 0xff;
oob[OOB_JFFS2_ECC5] = 0xff;
return 0;
}
