void CPU_TS_TmrInit (void) { CPU_INT32U fclk_freq; fclk_freq = CSP_PM_CPU_ClkFreqGet(); BSP_REG_DEMCR |= DEF_BIT_24; BSP_REG_DWT_CR |= DEF_BIT_00; CPU_TS_TmrFreqSet((CPU_TS_TMR_FREQ)fclk_freq); }
void CPU_TS_TmrInit (void) { CPU_INT32U cpu_clk_freq_hz; DEM_CR |= (CPU_INT32U)DEM_CR_TRCENA; /* Enable Cortex-M3's DWT CYCCNT reg. */ DWT_CYCCNT = (CPU_INT32U)0u; DWT_CR |= (CPU_INT32U)DWT_CR_CYCCNTENA; cpu_clk_freq_hz = BSP_CPU_ClkFreq(); CPU_TS_TmrFreqSet(cpu_clk_freq_hz); }
void CPU_TS_TmrInit (void) { CPU_INT32U fclk_freq; fclk_freq = BSP_CPU_ClkFreq(); BSP_REG_DEM_CR |= (CPU_INT32U)BSP_BIT_DEM_CR_TRCENA; /* Enable Cortex-M4's DWT CYCCNT reg. */ BSP_REG_DWT_CYCCNT = (CPU_INT32U)0u; BSP_REG_DWT_CR |= (CPU_INT32U)BSP_BIT_DWT_CR_CYCCNTENA; CPU_TS_TmrFreqSet((CPU_TS_TMR_FREQ)fclk_freq); }
void CPU_TS_TmrInit (void) { CPU_INT32U fclk_freq; fclk_freq = CSP_PM_CPU_ClkFreqGet(); CPU_PMU_En(); CPU_PMU_CtrCycleEn(); /* Enable counter cycle counter. */ CPU_PMU_CtrCycleRst(); /* Reset counter cycle counter. */ CPU_TS_TmrFreqSet((CPU_TS_TMR_FREQ)fclk_freq); /* Set TS tmr frequency */ }
static void AppTaskStart (void *p_arg) { CPU_INT32U clk_freq; CPU_INT32U ulPHYMR0; CPU_INT32U cnts; OS_ERR err; (void)&p_arg; BSP_Init(); /* Initialize BSP functions */ CPU_Init(); /* Initialize the uC/CPU services */ SysCtlPeripheralEnable(SYSCTL_PERIPH_ETH); /* Enable and Reset the Ethernet Controller. */ SysCtlPeripheralReset(SYSCTL_PERIPH_ETH); ulPHYMR0 = EthernetPHYRead(ETH_BASE, PHY_MR0); /* Power Down PHY */ EthernetPHYWrite(ETH_BASE, PHY_MR0, ulPHYMR0 | PHY_MR0_PWRDN); SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_ETH); clk_freq = BSP_CPUClkFreq(); /* Determine SysTick reference freq. */ cnts = clk_freq / (CPU_INT32U)OSCfg_TickRate_Hz; /* Determine nbr SysTick increments */ OS_CPU_SysTickInit(cnts); /* Init uC/OS periodic time src (SysTick). */ CPU_TS_TmrFreqSet(clk_freq); // #if(MICROSD_EN == 1) /* Mount the file system, using logical disk 0 */ //f_mount(0, &g_sFatFs); /* Create a new log.txt file */ //CmdLineProcess(g_cCmdBuf); // #endif /* Enable Wheel ISR Interrupt */ AppRobotMotorDriveSensorEnable(); /* Call your API here */ OSTaskCreateNew((OS_TCB *)&AppTaskOneTCB, (CPU_CHAR *)"App Task One", (OS_TASK_PTR ) AppTaskOne, (void *) 0, (OS_PRIO ) APP_TASK_ONE_PRIO, (CPU_STK *)&AppTaskOneStk[0], (CPU_STK_SIZE) APP_TASK_ONE_STK_SIZE / 10u, (CPU_STK_SIZE) APP_TASK_ONE_STK_SIZE, (OS_MSG_QTY ) 0u, (OS_TICK ) 0u, (void *)(CPU_INT32U) 1, (OS_OPT )(OS_OPT_TASK_STK_CHK | OS_OPT_TASK_STK_CLR), (OS_ERR *)&err, (OS_PERIOD) 5000); OSTaskCreateNew((OS_TCB *)&AppTaskTwoTCB, (CPU_CHAR *)"App Task Two", (OS_TASK_PTR ) AppTaskTwo, (void *) 0, (OS_PRIO ) APP_TASK_TWO_PRIO, (CPU_STK *)&AppTaskTwoStk[0], (CPU_STK_SIZE) APP_TASK_TWO_STK_SIZE / 10u, (CPU_STK_SIZE) APP_TASK_TWO_STK_SIZE, (OS_MSG_QTY ) 0u, (OS_TICK ) 0u, (void *) (CPU_INT32U) 2, (OS_OPT )(OS_OPT_TASK_STK_CHK | OS_OPT_TASK_STK_CLR), (OS_ERR *)&err,(OS_PERIOD) 7000); OSTaskCreateNew((OS_TCB *)&AppTaskThreeTCB, (CPU_CHAR *)"App Task Three", (OS_TASK_PTR ) AppTaskThree, (void *) 0, (OS_PRIO ) APP_TASK_THREE_PRIO, (CPU_STK *)&AppTaskThreeStk[0], (CPU_STK_SIZE) APP_TASK_THREE_STK_SIZE / 10u, (CPU_STK_SIZE) APP_TASK_THREE_STK_SIZE, (OS_MSG_QTY ) 0u, (OS_TICK ) 0u, (void *)(CPU_INT32U) 3, (OS_OPT )(OS_OPT_TASK_STK_CHK | OS_OPT_TASK_STK_CLR), (OS_ERR *)&err, (OS_PERIOD) 7000); OSTaskCreateNew((OS_TCB *)&AppTaskFourTCB, (CPU_CHAR *)"App Task Four", (OS_TASK_PTR ) AppTaskFour, (void *) 0, (OS_PRIO ) APP_TASK_FOUR_PRIO, (CPU_STK *)&AppTaskFourStk[0], (CPU_STK_SIZE) APP_TASK_FOUR_STK_SIZE / 10u, (CPU_STK_SIZE) APP_TASK_FOUR_STK_SIZE, (OS_MSG_QTY ) 0u, (OS_TICK ) 0u, (void *) (CPU_INT32U) 4, (OS_OPT )(OS_OPT_TASK_STK_CHK | OS_OPT_TASK_STK_CLR), (OS_ERR *)&err,(OS_PERIOD) 10000); OSTaskDel((OS_TCB *)0, &err); }
static void AppTaskStart (void *p_arg) { CPU_INT32U clk_freq; CPU_INT32U cnts; OS_ERR err; (void)&p_arg; BSP_Init(); /* Initialize BSP functions */ CPU_Init(); /* Initialize the uC/CPU services */ clk_freq = BSP_CPU_ClkFreq(); /* Determine SysTick reference freq. */ cnts = clk_freq / (CPU_INT32U)OSCfg_TickRate_Hz; /* Determine nbr SysTick increments */ OS_CPU_SysTickInit(cnts); /* Init uC/OS periodic time src (SysTick). */ CPU_TS_TmrFreqSet(clk_freq); #if (OS_CFG_STAT_TASK_EN > 0u) OSStatTaskCPUUsageInit(&err); /* Compute CPU capacity with no task running */ #endif CPU_IntDisMeasMaxCurReset(); App_ProbeInit(); BSP_LED_On(1); BSP_LED_Off(2); AppDisplayTaskCreate(); while (DEF_ON) { /* Task body, always written as an infinite loop. */ OSTimeDlyHMSM(0u, 0u, 1u, 0u, OS_OPT_TIME_HMSM_STRICT, &err); BSP_LED_Toggle(0); /* Toggle both LEDs every second. */ bLED[0] ^= DEF_TRUE; bLED[1] ^= DEF_TRUE; } }
void CPU_TS_TmrInit (void) { CPU_INT32U fclk_freq; CPU_INT32U reg_val; /* ---- DWT WRITE ACCESS UNLOCK (CORTEX-M7 ONLY!!) ---- */ reg_val = CPU_BSP_REG_DWT_LSR; /* Read lock status register. */ if ((reg_val & CPU_BSP_BIT_DWT_LSR_SLI) != 0) { /* Check if Software lock control mecanism exits */ if ((reg_val & CPU_BSP_BIT_DWT_LSR_SLK) != 0) { /* Check if DWT access needs to be unlocked */ CPU_BSP_REG_DWT_LAR = CPU_BSP_DWT_LAR_KEY; /* Unlock DWT write access. */ } } fclk_freq = BSP_ClkFreqGet(BSP_CLK_ID_HCLK); CPU_BSP_REG_DEMCR |= DEF_BIT_24; /* Set DEM_CR_TRCENA */ CPU_BSP_REG_DWT_CYCCNT = 0u; CPU_BSP_REG_DWT_CR |= DEF_BIT_00; /* Set DWT_CR_CYCCNTENA */ CPU_TS_TmrFreqSet((CPU_TS_TMR_FREQ)fclk_freq); }