/**
* ============================================================================
* @n@b Osal_biosMultiCoreCsExit
*
* @b brief
* @n This API needs to be called to exit a previously
* acquired critical section lock using @a Osal_biosMultiCoreCsEnter ()
* API. It resets the multi-core lock, enabling another process/core
* to grab it.
*
* @param[in] None
*
* @return None
* =============================================================================
*/
Void Osal_biosMultiCoreCsExit ()
{
/* Release the hardware semaphore
*
* Release multi-core lock.
*/
CSL_semReleaseSemaphore (FFTC_HW_SEM);
return;
}
void Osal_platformSpiCsExit (void)
{
/* Release the hardware semaphore
*
* Release multi-core lock.
*/
CSL_semReleaseSemaphore (PLATFORM_SPI_HW_SEM);
return;
}
void deeplearn(short* data, uint32_t w, uint32_t h)
{
core_id = DNUM;
MemMgr_HeapInit(w,h);
if(DNUM==MASTER_CORE_ID)
{
INIT_DONE = 0x0;
}
operateLayer1(data, w, h);
CACHE_wbAllL1dWait();
/* All cores update the counter informing that they finished their iteration */
while ((CSL_semAcquireDirect (LAYER_1_SEM)) == 0);
L1_SYNC = L1_SYNC+1;
/* Release the hardware semaphore. */
CSL_semReleaseSemaphore (LAYER_1_SEM);
/* All cores wait here to sync up */
while (L1_SYNC != NUM_CORES);
operateLayer2(w / 2, h / 2);
CACHE_wbAllL1dWait();
/* All cores update the counter informing that they finished their iteration */
while ((CSL_semAcquireDirect (LAYER_2_SEM)) == 0);
L2_SYNC = L2_SYNC+1;
/* Release the hardware semaphore. */
CSL_semReleaseSemaphore (LAYER_2_SEM);
/* All cores wait here to sync up */
while (L2_SYNC != NUM_CORES);
}
/**
* ============================================================================
* @n@b Osal_qmssCsExit
*
* @b brief
* @n This API needs to be called to exit a previously
* acquired critical section lock using @a Osal_fftcQmssCsEnter ()
* API. It resets the multi-core and multi-threaded lock,
* enabling another process/core to grab QMSS access.
*
* @param[in] CsHandle
* Handle for unlocking critical section.
*
* @return None
* =============================================================================
*/
Void Osal_qmssCsExit (Void* CsHandle)
{
/* Enable all interrupts and enables the OS scheduler back on.
*
* Release multi-threaded / multi-process lock on this core.
*/
Hwi_restore(coreKey [CSL_chipReadDNUM ()]);
/* Release the hardware semaphore
*
* Release multi-core lock.
*/
CSL_semReleaseSemaphore (QMSS_HW_SEM);
return;
}
void deeplearn(short* data, uint32_t w, uint32_t h)
{
core_id = DNUM;
MemMgr_HeapInit(w,h);
operateLayer1(data, w, h);
CACHE_wbAllL1dWait();
/* All cores update the counter informing that they finished their iteration */
while ((CSL_semAcquireDirect (LAYER_1_SEM)) == 0);
maps_info_ptr->layer1_sync++;
/* Release the hardware semaphore. */
CSL_semReleaseSemaphore (LAYER_1_SEM);
/* All cores wait here to sync up */
while (maps_info_ptr->layer1_sync != NUM_CORES);
if(DNUM==MASTER_CORE_ID)
CSL_semAcquireDirect(INIT_DONE_SEM);
operateLayer2(w / 2, h / 2);
CACHE_wbAllL1dWait();
// /* All cores update the counter informing that they finished their iteration */
// while ((CSL_semAcquireDirect (LAYER_2_SEM)) == 0);
//
// maps_info_ptr->layer2_sync++;
//
// /* Release the hardware semaphore. */
// CSL_semReleaseSemaphore (LAYER_2_SEM);
//
// /* All cores wait here to sync up */
// while (maps_info_ptr->layer2_sync != 0x8);
// dummy classifier
//dummy_classifier(pInputNeurons, 50*9, 64, 10, pInputWt, pHiddenBias, pOutputWt);
}
/**
* @b Description
* @n
* The function is used to exit a critical section
* protected using Osal_qmssCsEnter() API.
*
* @param[in] CsHandle
* Handle for unlocking critical section.
*
* @retval
* Not Applicable
*/
Void Osal_qmssCsExit (Ptr CsHandle)
{
/* Release the hardware semaphore */
CSL_semReleaseSemaphore (QMSS_HW_SEM);
return;
}
/**
* @b Description
* @n
* The function is used to exit a critical section
* protected using Osal_cppiCsEnter() API.
*
* @param[in] CsHandle
* Handle for unlocking critical section.
*
* @retval
* Not Applicable
*/
Void Osal_cppiCsExit (Ptr CsHandle)
{
/* Release the hardware semaphore */
CSL_semReleaseSemaphore (CPPI_HW_SEM);
return;
}
/**
* @b Description
* @n
* The function is called to end the critical section which was protecting
* shared resources from access across multiple cores.
*
* @param[in] critSectHandle
* Semaphore opaque handle.
*
* @retval
* None
*/
Void Osal_srioExitMultipleCoreCriticalSection(Void* critSectHandle)
{
CSL_semReleaseSemaphore (SRIO_HW_SEM);
}
void MemMgr_HeapInit(uint32_t img_width, uint32_t img_height)
{
int num_core,l1_width,l1_height;
int l2_width,l2_height;
int iN,hN,oN;
alloc_info msmc_info,l2_info;
l1_width = img_width/L1_DOWN_SIZE_FACTOR;
l1_height = img_height/L1_DOWN_SIZE_FACTOR;
l2_width = l1_width/L2_DOWN_SIZE_FACTOR;
l2_height = l1_height/L2_DOWN_SIZE_FACTOR;
l1_size = l1_width*l1_height;
l2_size = l2_width*l2_height;
if(DNUM==MASTER_CORE_ID)
{
msmc_info.free_ptr = (char*)MSMC_REG_BASE;
msmc_info.block_count = 0;
msmc_info.block_size = CACHE_L2_LINESIZE;
msmc_info.max_size = MSMC_SRAM_SIZE;
msmc_info.max_blocks = MSMC_SRAM_SIZE/CACHE_L2_LINESIZE;
for(num_core=0; num_core<NUM_CORES;num_core++)
{
#ifndef FULLY_CONNECTED
maps_info_ptr->l1_maps_ptr[num_core] = mem_alloc(&smem_info,l1_width*l1_height*maps_info_ptr->l1_maps[num_core]*sizeof(short)); ///*TODO*/data allignment
while(maps_info_ptr->l1_maps_ptr[num_core]==NULL);
#else
maps_info_ptr->l1_maps_ptr[num_core] = mem_alloc(&smem_info,l1_width*l1_height*sizeof(short)); ///*TODO*/data allignment
while(maps_info_ptr->l1_maps_ptr[num_core]==NULL);
#endif
}
for(num_core=0; num_core<NUM_CORES;num_core++)
{
maps_info_ptr->l2_maps_ptr[num_core] = mem_alloc(&smem_info,l2_width*l2_height*maps_info_ptr->l2_maps[num_core]*sizeof(short));
while(maps_info_ptr->l2_maps_ptr[num_core]==NULL);
}
while ((CSL_semAcquireDirect (LAYER_1_SEM)) == 0);
/* The core has completed local initialization */
maps_info_ptr->layer1_sync = 0;
/* Release the hardware semaphore. */
CSL_semReleaseSemaphore ( LAYER_1_SEM);
while ((CSL_semAcquireDirect (LAYER_2_SEM)) == 0);
/* The core has completed local initialization */
maps_info_ptr->layer2_sync = 0;
/* Release the hardware semaphore. */
CSL_semReleaseSemaphore ( LAYER_2_SEM);
CSL_semReleaseSemaphore(INIT_DONE_SEM);
}
while(!CSL_semIsFree(INIT_DONE_SEM));
l2_info.free_ptr = (char*)L2_HEAP_BASE;
l2_info.block_count = 0;
l2_info.block_size = CACHE_L1D_LINESIZE;
l2_info.max_size = L2_HEAP_SIZE;
l2_info.max_blocks = L2_HEAP_SIZE/CACHE_L1D_LINESIZE;
temp_img_ptr = mem_alloc(&l2_info,img_width*img_height*sizeof(short));
while(temp_img_ptr==NULL);
layer1_ptr = mem_alloc(&l2_info,l1_width*l1_height*sizeof(short));
while(layer1_ptr==NULL);
temp1_ptr = mem_alloc(&l2_info,l1_width*l1_height*sizeof(short));
while(temp1_ptr==NULL);
if(DNUM == MASTER_CORE_ID)
{
//W3 = 12; H3 = 12; K3 = 5; N3 = 64;
//iN = N3 * ((W3 - K3 + 1)/2) * ((H3 - K3 + 1)/2);
iN = 50*9;
hN = 64;
oN = 10;
pInputNeurons = mem_alloc(&l2_info,iN*sizeof(float));
while(pInputNeurons==NULL);
pInputWt = mem_alloc(&l2_info,hN*iN*sizeof(float));
while(pInputWt==NULL);
pHiddenBias = mem_alloc(&l2_info,hN*sizeof(float));
while(pHiddenBias==NULL);
pOutputWt = mem_alloc(&l2_info,hN*oN*sizeof(float));
while(pOutputWt==NULL);
}
local_l1_maps_ptr= (short*)maps_info_ptr->l1_maps_ptr[DNUM];
local_l2_maps_ptr= (short*)maps_info_ptr->l2_maps_ptr[DNUM];
}
void MemMgr_HeapInit(uint32_t img_width, uint32_t img_height)
{
int num_core,l1_width,l1_height;
int l2_width,l2_height;
alloc_info msmc_info,l2_info;
int locmem_size;
l1_width = img_width/L1_DOWN_SIZE_FACTOR;
l1_height = img_height/L1_DOWN_SIZE_FACTOR;
l2_width = l1_width/L2_DOWN_SIZE_FACTOR;
l2_height = l1_height/L2_DOWN_SIZE_FACTOR;
l1_size = l1_width*l1_height*sizeof(short);
l2_size = l2_width*l2_height*sizeof(short);
if(DNUM==MASTER_CORE_ID)
{
msmc_info.free_ptr = (char*)MSMC_REG_BASE;
msmc_info.block_count = 0;
msmc_info.block_size = CACHE_L2_LINESIZE;
msmc_info.max_size = MSMC_SRAM_SIZE;
msmc_info.max_blocks = MSMC_SRAM_SIZE/CACHE_L2_LINESIZE;
memset((void*)MSMC_REG_BASE,0x0,MSMC_SRAM_SIZE);
for(num_core=0; num_core<NUM_CORES;num_core++)
{
maps_info_ptr->l1_maps_ptr[num_core] = mem_alloc(&msmc_info,l1_width*l1_height*maps_info_ptr->l1_maps[num_core]*sizeof(short));
while(maps_info_ptr->l1_maps_ptr[num_core]==NULL);
}
for(num_core=0; num_core<NUM_CORES;num_core++)
{
maps_info_ptr->l2_maps_ptr[num_core] = mem_alloc(&msmc_info,l2_width*l2_height*maps_info_ptr->l2_maps[num_core]*sizeof(short));
while(maps_info_ptr->l2_maps_ptr[num_core]==NULL);
}
while ((CSL_semAcquireDirect (LAYER_1_SEM)) == 0);
/* The core has completed local initialization */
L1_SYNC = 0;
/* Release the hardware semaphore. */
CSL_semReleaseSemaphore ( LAYER_1_SEM);
while ((CSL_semAcquireDirect (LAYER_2_SEM)) == 0);
/* The core has completed local initialization */
L2_SYNC = 0;
/* Release the hardware semaphore. */
CSL_semReleaseSemaphore ( LAYER_2_SEM);
INIT_DONE = 0x1;
}
while(INIT_DONE==0x0);
l2_info.free_ptr = (char*)L2_HEAP_BASE;
l2_info.block_count = 0;
l2_info.block_size = CACHE_L1D_LINESIZE;
l2_info.max_size = L2_HEAP_SIZE;
l2_info.max_blocks = L2_HEAP_SIZE/CACHE_L1D_LINESIZE;
memset((void*)L2_HEAP_BASE,0x0,L2_HEAP_SIZE);
locmem_size = (img_width*img_height*sizeof(short))+(3*l1_size);
if(locmem_size>L2_HEAP_SIZE)
{
printf("Insufficient l2 memory \n");
while(1);
}
temp_img_ptr = mem_alloc(&l2_info,img_width*img_height*sizeof(short));
layer1_ptr = mem_alloc(&l2_info,l1_width*l1_height*sizeof(short));
temp1_ptr = mem_alloc(&l2_info,l1_width*l1_height*sizeof(short));
temp2_ptr = mem_alloc(&l2_info,l1_width*l1_height*sizeof(short));
local_l1_maps_ptr= (short*)maps_info_ptr->l1_maps_ptr[DNUM];
local_l2_maps_ptr= (short*)maps_info_ptr->l2_maps_ptr[DNUM];
}
