void omap_free_dma(int lch) { unsigned long flags; if (dma_chan[lch].dev_id == -1) { IOLog("omap_dma: trying to free unallocated DMA channel %d\n", lch); return; } if (cpu_class_is_omap1()) { /* Disable all DMA interrupts for the channel. */ dma_write(0, CICR(lch)); /* Make sure the DMA transfer is stopped. */ dma_write(0, CCR(lch)); } if (cpu_class_is_omap2()) { u32 val; spin_lock_irqsave(&dma_chan_lock, flags); /* Disable interrupts */ val = dma_read(IRQENABLE_L0); val &= ~(1 << lch); dma_write(val, IRQENABLE_L0); spin_unlock_irqrestore(&dma_chan_lock, flags); /* Clear the CSR register and IRQ status register */ dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch)); dma_write(1 << lch, IRQSTATUS_L0); /* Disable all DMA interrupts for the channel. */ dma_write(0, CICR(lch)); /* Make sure the DMA transfer is stopped. */ dma_write(0, CCR(lch)); omap_clear_dma(lch); } spin_lock_irqsave(&dma_chan_lock, flags); dma_chan[lch].dev_id = -1; dma_chan[lch].next_lch = -1; dma_chan[lch].callback = NULL; spin_unlock_irqrestore(&dma_chan_lock, flags); }
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int mode) { struct atmel_spi_slave *as; unsigned int scbr; u32 csrx; void *regs; if (!spi_cs_is_valid(bus, cs)) return NULL; switch (bus) { case 0: regs = (void *)ATMEL_BASE_SPI0; break; #ifdef ATMEL_BASE_SPI1 case 1: regs = (void *)ATMEL_BASE_SPI1; break; #endif #ifdef ATMEL_BASE_SPI2 case 2: regs = (void *)ATMEL_BASE_SPI2; break; #endif #ifdef ATMEL_BASE_SPI3 case 3: regs = (void *)ATMEL_BASE_SPI3; break; #endif default: return NULL; } scbr = (get_spi_clk_rate(bus) + max_hz - 1) / max_hz; if (scbr > ATMEL_SPI_CSRx_SCBR_MAX) /* Too low max SCK rate */ return NULL; if (scbr < 1) scbr = 1; csrx = ATMEL_SPI_CSRx_SCBR(scbr); csrx |= ATMEL_SPI_CSRx_BITS(ATMEL_SPI_BITS_8); if (!(mode & SPI_CPHA)) csrx |= ATMEL_SPI_CSRx_NCPHA; if (mode & SPI_CPOL) csrx |= ATMEL_SPI_CSRx_CPOL; as = spi_alloc_slave(struct atmel_spi_slave, bus, cs); if (!as) return NULL; as->regs = regs; as->mr = ATMEL_SPI_MR_MSTR | ATMEL_SPI_MR_MODFDIS | ATMEL_SPI_MR_PCS(~(1 << cs) & 0xf); if (spi_has_wdrbt(as)) as->mr |= ATMEL_SPI_MR_WDRBT; spi_writel(as, CSR(cs), csrx); return &as->slave; }
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int mode) { struct atmel_spi_slave *as; unsigned int scbr; u32 csrx; void *regs; if (cs > 3 || !spi_cs_is_valid(bus, cs)) return NULL; switch (bus) { case 0: regs = (void *)SPI0_BASE; break; #ifdef SPI1_BASE case 1: regs = (void *)SPI1_BASE; break; #endif #ifdef SPI2_BASE case 2: regs = (void *)SPI2_BASE; break; #endif #ifdef SPI3_BASE case 3: regs = (void *)SPI3_BASE; break; #endif default: return NULL; } scbr = (get_spi_clk_rate(bus) + max_hz - 1) / max_hz; if (scbr > ATMEL_SPI_CSRx_SCBR_MAX) /* Too low max SCK rate */ return NULL; if (scbr < 1) scbr = 1; csrx = ATMEL_SPI_CSRx_SCBR(scbr); csrx |= ATMEL_SPI_CSRx_BITS(ATMEL_SPI_BITS_8); if (!(mode & SPI_CPHA)) csrx |= ATMEL_SPI_CSRx_NCPHA; if (mode & SPI_CPOL) csrx |= ATMEL_SPI_CSRx_CPOL; as = malloc(sizeof(struct atmel_spi_slave)); if (!as) return NULL; as->slave.bus = bus; as->slave.cs = cs; as->regs = regs; as->mr = ATMEL_SPI_MR_MSTR | ATMEL_SPI_MR_MODFDIS | ATMEL_SPI_MR_PCS(~(1 << cs) & 0xf); spi_writel(as, CSR(cs), csrx); return &as->slave; }
int omap_request_dma(int dev_id, const char *dev_name, void (*callback)(int lch, u16 ch_status, void *data), void *data, int *dma_ch_out) { int ch, free_ch = -1; unsigned long flags; struct omap_dma_lch *chan; spin_lock_irqsave(&dma_chan_lock, flags); for (ch = 0; ch < dma_chan_count; ch++) { if (free_ch == -1 && dma_chan[ch].dev_id == -1) { free_ch = ch; if (dev_id == 0) break; } } if (free_ch == -1) { spin_unlock_irqrestore(&dma_chan_lock, flags); return -EBUSY; } chan = dma_chan + free_ch; chan->dev_id = dev_id; if (cpu_class_is_omap1()) clear_lch_regs(free_ch); if (cpu_class_is_omap2()) omap_clear_dma(free_ch); spin_unlock_irqrestore(&dma_chan_lock, flags); chan->dev_name = dev_name; chan->callback = callback; chan->data = data; chan->flags = 0; #ifndef CONFIG_ARCH_OMAP1 if (cpu_class_is_omap2()) { chan->chain_id = -1; chan->next_linked_ch = -1; } #endif chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ; if (cpu_class_is_omap1()) chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ; else if (cpu_class_is_omap2()) chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ | OMAP2_DMA_TRANS_ERR_IRQ; if (cpu_is_omap16xx()) { /* If the sync device is set, configure it dynamically. */ if (dev_id != 0) { set_gdma_dev(free_ch + 1, dev_id); dev_id = free_ch + 1; } /* * Disable the 1510 compatibility mode and set the sync device * id. */ dma_write(dev_id | (1 << 10), CCR(free_ch)); } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) { dma_write(dev_id, CCR(free_ch)); } if (cpu_class_is_omap2()) { omap2_enable_irq_lch(free_ch); omap_enable_channel_irq(free_ch); /* Clear the CSR register and IRQ status register */ dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch)); dma_write(1 << free_ch, IRQSTATUS_L0); } *dma_ch_out = free_ch; return 0; }