static void
pnphy_status(struct mii_softc *sc)
{
struct mii_data *mii = sc->mii_pdata;
int reg;
struct dc_softc *dc_sc;
dc_sc = mii->mii_ifp->if_softc;
mii->mii_media_status = IFM_AVALID;
mii->mii_media_active = IFM_ETHER;
reg = CSR_READ_4(dc_sc, DC_ISR);
if (!(reg & DC_ISR_LINKFAIL))
mii->mii_media_status |= IFM_ACTIVE;
if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_SPEEDSEL)
mii->mii_media_active |= IFM_10_T;
else
mii->mii_media_active |= IFM_100_TX;
if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_FULLDUPLEX)
mii->mii_media_active |= IFM_FDX;
else
mii->mii_media_active |= IFM_HDX;
}
static void
bfe_core_reset( struct bfe_softc * sc )
{
u_int32_t val;
/* Disable the core */
bfe_core_disable(sc);
/* and bring it back up */
CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC));
CSR_READ_4(sc, BFE_SBTMSLOW);
DELAY(10);
/* Chip bug, clear SERR, IB and TO if they are set. */
if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR)
CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0);
val = CSR_READ_4(sc, BFE_SBIMSTATE);
if (val & (BFE_IBE | BFE_TO))
CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO));
/* Clear reset and allow it to move through the core */
CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC));
CSR_READ_4(sc, BFE_SBTMSLOW);
DELAY(10);
/* Leave the clock set */
CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK);
CSR_READ_4(sc, BFE_SBTMSLOW);
DELAY(10);
}
/* Set a specific pin's in/out state. */
static int
aml8726_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
{
struct aml8726_gpio_softc *sc = device_get_softc(dev);
uint32_t mask = 1U << pin;
if (pin >= sc->npins)
return (EINVAL);
AML_GPIO_LOCK(sc);
if ((flags & GPIO_PIN_OUTPUT) != 0) {
/* Output. Turn on driver. */
CSR_WRITE_4(sc, AML_GPIO_OE_N_REG,
(CSR_READ_4(sc, AML_GPIO_OE_N_REG) & ~mask));
} else {
/* Input. Turn off driver. */
CSR_WRITE_4(sc, AML_GPIO_OE_N_REG,
(CSR_READ_4(sc, AML_GPIO_OE_N_REG) | mask));
}
AML_GPIO_UNLOCK(sc);
return (0);
}
static int
kr_miibus_writereg(device_t dev, int phy, int reg, int data)
{
struct kr_softc * sc = device_get_softc(dev);
int i;
i = KR_MII_TIMEOUT;
while ((CSR_READ_4(sc, KR_MIIMIND) & KR_MIIMIND_BSY) && i)
i--;
if (i == 0)
device_printf(dev, "phy mii is busy %d:%d\n", phy, reg);
CSR_WRITE_4(sc, KR_MIIMADDR, (phy << 8) | reg);
i = KR_MII_TIMEOUT;
while ((CSR_READ_4(sc, KR_MIIMIND) & KR_MIIMIND_BSY) && i)
i--;
if (i == 0)
device_printf(dev, "phy mii is busy %d:%d\n", phy, reg);
CSR_WRITE_4(sc, KR_MIIMWTD, data);
i = KR_MII_TIMEOUT;
while ((CSR_READ_4(sc, KR_MIIMIND) & KR_MIIMIND_BSY) && i)
i--;
if (i == 0)
device_printf(dev, "phy mii is busy %d:%d\n", phy, reg);
return (0);
}
static void
pcn_getfactaddr(pcn_t *pcnp)
{
uint32_t addr[2];
addr[0] = CSR_READ_4(pcnp, PCN_IO32_APROM00);
addr[1] = CSR_READ_4(pcnp, PCN_IO32_APROM01);
bcopy(&addr[0], &pcnp->pcn_addr[0], sizeof (pcnp->pcn_addr));
}
static void
dcphy_status(struct mii_softc *sc)
{
struct mii_data *mii = sc->mii_pdata;
int reg, anlpar, tstat = 0;
struct dc_softc *dc_sc;
dc_sc = mii->mii_ifp->if_softc;
mii->mii_media_status = IFM_AVALID;
mii->mii_media_active = IFM_ETHER;
if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
return;
reg = CSR_READ_4(dc_sc, DC_10BTSTAT);
if (!(reg & DC_TSTAT_LS10) || !(reg & DC_TSTAT_LS100))
mii->mii_media_status |= IFM_ACTIVE;
if (CSR_READ_4(dc_sc, DC_10BTCTRL) & DC_TCTL_AUTONEGENBL) {
/* Erg, still trying, I guess... */
tstat = CSR_READ_4(dc_sc, DC_10BTSTAT);
if ((tstat & DC_TSTAT_ANEGSTAT) != DC_ASTAT_AUTONEGCMP) {
if ((DC_IS_MACRONIX(dc_sc) || DC_IS_PNICII(dc_sc)) &&
(tstat & DC_TSTAT_ANEGSTAT) == DC_ASTAT_DISABLE)
goto skip;
mii->mii_media_active |= IFM_NONE;
return;
}
if (tstat & DC_TSTAT_LP_CAN_NWAY) {
anlpar = tstat >> 16;
if (anlpar & ANLPAR_TX_FD &&
sc->mii_capabilities & BMSR_100TXFDX)
mii->mii_media_active |= IFM_100_TX | IFM_FDX;
else if (anlpar & ANLPAR_T4 &&
sc->mii_capabilities & BMSR_100T4)
mii->mii_media_active |= IFM_100_T4 | IFM_HDX;
else if (anlpar & ANLPAR_TX &&
sc->mii_capabilities & BMSR_100TXHDX)
mii->mii_media_active |= IFM_100_TX | IFM_HDX;
else if (anlpar & ANLPAR_10_FD)
mii->mii_media_active |= IFM_10_T | IFM_FDX;
else if (anlpar & ANLPAR_10)
mii->mii_media_active |= IFM_10_T | IFM_HDX;
else
mii->mii_media_active |= IFM_NONE;
if (DC_IS_INTEL(dc_sc))
DC_CLRBIT(dc_sc, DC_10BTCTRL,
DC_TCTL_AUTONEGENBL);
return;
}
/* special I/O functions */
static __inline u_int32_t
_bs_r(void *v, bus_space_handle_t ioh, bus_size_t off, u_int32_t be)
{
u_int32_t data;
CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3);
CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_READ);
data = CSR_READ_4(PCI_NP_RDATA);
if (CSR_READ_4(PCI_ISR) & ISR_PFE)
CSR_WRITE_4(PCI_ISR, ISR_PFE);
return data;
}
static void
dump_regs(Environ *e, Self *s)
{
dprintf("\n");
dprintf("ethxpro: scb_rus/scb_cus: %#x\n", CSR_READ_1(s, CSR_SCB_RUSCUS));
dprintf("ethxpro: scb_statack: %#x\n", CSR_READ_1(s, CSR_SCB_STATACK));
dprintf("ethxpro: scb_command: %#x\n", CSR_READ_1(s, CSR_SCB_COMMAND));
dprintf("ethxpro: scb_intrcntl: %#x\n", CSR_READ_1(s, CSR_SCB_INTRCNTL));
dprintf("ethxpro: scb_general: %#x\n", CSR_READ_4(s, CSR_SCB_GENERAL));
dprintf("ethxpro: port: %#x\n", CSR_READ_4(s, CSR_PORT));
dprintf("ethxpro: flash control: %#x\n", CSR_READ_2(s, CSR_FLASHCONTROL));
dprintf("ethxpro: eeprom ctrl: %#x\n", CSR_READ_2(s, CSR_EEPROMCONTROL));
dprintf("ethxpro: mdi control: %#x\n", CSR_READ_4(s, CSR_MDICONTROL));
}
static void
aml8726_rng_harvest(void *arg)
{
struct aml8726_rng_softc *sc = arg;
uint32_t rn[2];
rn[0] = CSR_READ_4(sc, AML_RNG_0_REG);
rn[1] = CSR_READ_4(sc, AML_RNG_1_REG);
random_harvest(rn, sizeof(rn), sizeof(rn) * NBBY / 2,
RANDOM_PURE_AML8726);
callout_reset(&sc->co, sc->ticks, aml8726_rng_harvest, sc);
}
static void
bfe_clear_stats( struct bfe_softc * sc )
{
u_long reg;
BFE_LOCK(sc);
CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
CSR_READ_4(sc, reg);
for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
CSR_READ_4(sc, reg);
BFE_UNLOCK(sc);
}
static int
aml8726_usb_phy_detach(device_t dev)
{
struct aml8726_usb_phy_softc *sc = device_get_softc(dev);
uint32_t i;
uint32_t value;
/*
* Disable by issuing a power on reset.
*/
value = CSR_READ_4(sc, AML_USB_PHY_CFG_REG);
value |= (AML_USB_PHY_CFG_A_POR | AML_USB_PHY_CFG_B_POR);
CSR_WRITE_4(sc, AML_USB_PHY_CFG_REG, value);
CSR_BARRIER(sc, AML_USB_PHY_CFG_REG);
/* Turn off power */
i = sc->npwr_en;
while (i-- != 0) {
(void)GPIO_PIN_SET(sc->pwr_en[i].dev, sc->pwr_en[i].pin,
PIN_OFF_FLAG(sc->pwr_en[i].pol));
}
free (sc->pwr_en, M_DEVBUF);
sc->pwr_en = NULL;
bus_release_resources(dev, aml8726_usb_phy_spec, sc->res);
return (0);
}
static int
bfe_wait_bit( struct bfe_softc * sc, u_int32_t reg, u_int32_t bit,
u_long timeout, const int clear )
{
u_long i;
int use_sleep = 0;
/* jliu@Apple: long timeouts polls are done using a blocking wait */
if (timeout >= 10000) {
use_sleep = 1;
timeout /= 1000;
}
for (i = 0; i < timeout; i++) {
u_int32_t val = CSR_READ_4(sc, reg);
if (clear && !(val & bit))
break;
if (!clear && (val & bit))
break;
if (use_sleep)
IOSleep(10);
else
DELAY(10);
}
if (i == timeout) {
DEBUG_LOG("bfe%d: BUG! Timeout waiting for bit %08x of register "
"%x to %s.\n", sc->bfe_unit, bit, reg,
(clear ? "clear" : "set"));
return -1;
}
return 0;
}
void *
kse_init(unsigned tag, void *data)
{
struct local *l;
struct desc *txd, *rxd;
unsigned i, val, fdx;
uint8_t *en;
l = ALLOC(struct local, sizeof(struct desc)); /* desc alignment */
memset(l, 0, sizeof(struct local));
l->csr = DEVTOV(pcicfgread(tag, 0x10));
en = data;
i = CSR_READ_2(l, MARL);
en[0] = i;
en[1] = i >> 8;
i = CSR_READ_2(l, MARM);
en[2] = i;
en[3] = i >> 8;
i = CSR_READ_2(l, MARH);
en[4] = i;
en[5] = i >> 8;
printf("MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
en[0], en[1], en[2], en[3], en[4], en[5]);
CSR_WRITE_2(l, CIDR, 1);
mii_dealan(l, 5);
val = pcicfgread(tag, PCI_ID_REG);
if (PCI_PRODUCT(val) == 0x8841) {
val = CSR_READ_4(l, P1SR);
fdx = !!(val & (1U << 9));
printf("%s", (val & (1U << 8)) ? "100Mbps" : "10Mbps");
if (fdx)
printf("-FDX");
printf("\n");
}
txd = &l->txd;
rxd = &l->rxd[0];
rxd[0].xd0 = htole32(R0_OWN);
rxd[0].xd1 = htole32(FRAMESIZE);
rxd[0].xd2 = htole32(VTOPHYS(l->rxstore[0]));
rxd[0].xd3 = htole32(VTOPHYS(&rxd[1]));
rxd[1].xd0 = htole32(R0_OWN);
rxd[1].xd1 = htole32(R1_RER | FRAMESIZE);
rxd[1].xd2 = htole32(VTOPHYS(l->rxstore[1]));
rxd[1].xd3 = htole32(VTOPHYS(&rxd[0]));
l->rx = 0;
CSR_WRITE_4(l, TDLB, VTOPHYS(txd));
CSR_WRITE_4(l, RDLB, VTOPHYS(rxd));
CSR_WRITE_4(l, MDTXC, 07); /* stretch short, add CRC, Tx enable */
CSR_WRITE_4(l, MDRXC, 01); /* Rx enable */
CSR_WRITE_4(l, MDRSC, 01); /* start receiving */
return l;
}
/* Toggle a pin's output value. */
static int
aml8726_gpio_pin_toggle(device_t dev, uint32_t pin)
{
struct aml8726_gpio_softc *sc = device_get_softc(dev);
uint32_t mask;
if (pin >= sc->npins)
return (EINVAL);
/*
* The GPIOAO OUT bits occupy the upper word of the OEN register.
*/
if (rman_get_start(sc->res[1]) == rman_get_start(sc->res[0]))
pin += 16;
mask = 1U << pin;
AML_GPIO_LOCK(sc);
CSR_WRITE_4(sc, AML_GPIO_OUT_REG,
CSR_READ_4(sc, AML_GPIO_OUT_REG) ^ mask);
AML_GPIO_UNLOCK(sc);
return (0);
}
uint32_t
_pci_io_bs_r_4(void *v, bus_space_handle_t ioh, bus_size_t off)
{
uint32_t data;
int s;
PCI_CONF_LOCK(s);
CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3);
CSR_WRITE_4(PCI_NP_CBE, COMMAND_NP_IO_READ);
data = CSR_READ_4(PCI_NP_RDATA);
if (CSR_READ_4(PCI_ISR) & ISR_PFE)
CSR_WRITE_4(PCI_ISR, ISR_PFE);
PCI_CONF_UNLOCK(s);
return data;
}
int
pxa2x0_i2c_wait(struct pxa2x0_i2c_softc *sc, int bit, int flags)
{
uint32_t isr;
int error;
int i;
for (i = I2C_TIMEOUT; i >= 0; --i) {
isr = CSR_READ_4(sc, I2C_ISR);
if (isr & (bit | ISR_BED))
break;
delay(1);
}
if (isr & (ISR_BED | (bit & ISR_ALD)))
error = EIO;
else if (isr & (bit & ~ISR_ALD))
error = 0;
else
error = ETIMEDOUT;
CSR_WRITE_4(sc, I2C_ISR, isr);
return error;
}
static unsigned
jz4780_get_timecount(struct timecounter *tc)
{
struct jz4780_timer_softc *sc =
(struct jz4780_timer_softc *)tc->tc_priv;
return CSR_READ_4(sc, JZ_OST_CNT_LO);
}
static void
bfe_pci_setup( struct bfe_softc * sc, u_int32_t cores )
{
u_int32_t bar_orig, pci_rev, val;
bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4);
pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4);
pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK;
val = CSR_READ_4(sc, BFE_SBINTVEC);
val |= cores;
CSR_WRITE_4(sc, BFE_SBINTVEC, val);
val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2);
val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST;
CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val);
pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4);
}
static __inline void
_bs_w(void *v, bus_space_handle_t ioh, bus_size_t off,
u_int32_t be, u_int32_t data)
{
CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3);
CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_WRITE);
CSR_WRITE_4(PCI_NP_WDATA, data);
if (CSR_READ_4(PCI_ISR) & ISR_PFE)
CSR_WRITE_4(PCI_ISR, ISR_PFE);
}
uint16_t
_pci_io_bs_r_2(void *v, bus_space_handle_t ioh, bus_size_t off)
{
uint32_t data, n, be;
int s;
n = (ioh + off) % 4;
be = (0xf & ~((1U << n) | (1U << (n + 1)))) << NP_CBE_SHIFT;
PCI_CONF_LOCK(s);
CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3);
CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_READ);
data = CSR_READ_4(PCI_NP_RDATA);
if (CSR_READ_4(PCI_ISR) & ISR_PFE)
CSR_WRITE_4(PCI_ISR, ISR_PFE);
PCI_CONF_UNLOCK(s);
return data >> (8 * n);
}
int
__haiku_disable_interrupts(device_t dev)
{
struct vge_softc *sc = device_get_softc(dev);
if (CSR_READ_4(sc, VGE_ISR) == 0)
return 0;
CSR_WRITE_4(sc, VGE_IMR, 0x00000000);
return 1;
}
void
pxa2x0_i2c_reset(struct pxa2x0_i2c_softc *sc)
{
CSR_WRITE_4(sc, I2C_ICR, ICR_UR);
CSR_WRITE_4(sc, I2C_ISAR, 0);
CSR_WRITE_4(sc, I2C_ISR, ISR_ALL);
while (CSR_READ_4(sc, I2C_ICR) & ~ICR_UR)
continue;
CSR_WRITE_4(sc, I2C_ICR, sc->sc_icr);
}
int
pcn_quiesce(dev_info_t *dip)
{
pcn_t *pcnp;
if ((pcnp = ddi_get_soft_state(pcn_ssp, ddi_get_instance(dip))) == NULL)
return (DDI_FAILURE);
/* don't want to take the chance of blocking */
CSR_WRITE_4(pcnp, PCN_IO32_RAP, PCN_CSR_EXTCTL1);
CSR_WRITE_4(pcnp, PCN_IO32_RDP, CSR_READ_4(pcnp, PCN_IO32_RDP) &
~(PCN_EXTCTL1_SINTEN));
CSR_WRITE_4(pcnp, PCN_IO32_RAP, PCN_CSR_CSR);
CSR_WRITE_4(pcnp, PCN_IO32_RDP,
(CSR_READ_4(pcnp, PCN_IO32_RDP) & ~(PCN_CSR_INTEN)) |
PCN_CSR_STOP);
return (DDI_SUCCESS);
}
static uint32_t
pcn_bcr_read(pcn_t *pcnp, uint32_t reg)
{
uint32_t val;
mutex_enter(&pcnp->pcn_reglock);
CSR_WRITE_4(pcnp, PCN_IO32_RAP, reg);
val = CSR_READ_4(pcnp, PCN_IO32_BDP);
mutex_exit(&pcnp->pcn_reglock);
return (val);
}
static int
coremctl_mch_readreg(device_t dev, int reg, uint32_t *val)
{
struct coremctl_softc *sc = device_get_softc(dev);
if (sc->sc_mch == NULL)
return EOPNOTSUPP;
*val = CSR_READ_4(sc, reg);
return 0;
}
static int
kr_miibus_readreg(device_t dev, int phy, int reg)
{
struct kr_softc * sc = device_get_softc(dev);
int i, result;
i = KR_MII_TIMEOUT;
while ((CSR_READ_4(sc, KR_MIIMIND) & KR_MIIMIND_BSY) && i)
i--;
if (i == 0)
device_printf(dev, "phy mii is busy %d:%d\n", phy, reg);
CSR_WRITE_4(sc, KR_MIIMADDR, (phy << 8) | reg);
i = KR_MII_TIMEOUT;
while ((CSR_READ_4(sc, KR_MIIMIND) & KR_MIIMIND_BSY) && i)
i--;
if (i == 0)
device_printf(dev, "phy mii is busy %d:%d\n", phy, reg);
CSR_WRITE_4(sc, KR_MIIMCMD, KR_MIIMCMD_RD);
i = KR_MII_TIMEOUT;
while ((CSR_READ_4(sc, KR_MIIMIND) & KR_MIIMIND_BSY) && i)
i--;
if (i == 0)
device_printf(dev, "phy mii read is timed out %d:%d\n", phy,
reg);
if (CSR_READ_4(sc, KR_MIIMIND) & KR_MIIMIND_NV)
printf("phy mii readreg failed %d:%d: data not valid\n",
phy, reg);
result = CSR_READ_4(sc , KR_MIIMRDD);
CSR_WRITE_4(sc, KR_MIIMCMD, 0);
return (result);
}
static void
pcn_irq_en(device_t d)
{
struct pcn_softc *sc = device_get_softc(d);
/* This can be called from IRQ context -- since all register accesses
* involve RAP we must take care to preserve it across this routine!
*/
uint32_t rap = CSR_READ_4(sc, PCN_IO32_RAP);
/* do NOT |= INTEN since writing 1 in the wrong place may clear things */
pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN);
CSR_WRITE_4(sc, PCN_IO32_RAP, rap);
}
static void
bfe_core_disable( struct bfe_softc * sc )
{
if((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET)
return;
/*
* Set reject, wait for it set, then wait for the core to stop being busy
* Then set reset and reject and enable the clocks
*/
CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK));
bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 100000, 0);
bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 100000, 1);
CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT |
BFE_RESET));
CSR_READ_4(sc, BFE_SBTMSLOW);
DELAY(10);
/* Leave reset and reject set */
CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET));
CSR_READ_4(sc, BFE_SBTMSLOW);
DELAY(10);
}
static void
ecc_e31200_errlog_ch(struct ecc_e31200_softc *sc,
int err0_ofs, int err1_ofs, const char *desc)
{
uint32_t err0, err1;
err0 = CSR_READ_4(sc, err0_ofs);
if ((err0 & (MCH_E31200_ERRLOG0_CERRSTS | MCH_E31200_ERRLOG0_MERRSTS))
== 0)
return;
err1 = CSR_READ_4(sc, err1_ofs);
ecc_printf(sc, "%s error @bank %d, rank %d, chunk %d, syndrome %d, "
"row %d, col %d\n", desc,
__SHIFTOUT(err0, MCH_E31200_ERRLOG0_ERRBANK),
__SHIFTOUT(err0, MCH_E31200_ERRLOG0_ERRRANK),
__SHIFTOUT(err0, MCH_E31200_ERRLOG0_ERRCHUNK),
__SHIFTOUT(err0, MCH_E31200_ERRLOG0_ERRSYND),
__SHIFTOUT(err1, MCH_E31200_ERRLOG1_ERRROW),
__SHIFTOUT(err1, MCH_E31200_ERRLOG1_ERRCOL));
}
void
ste_wait(struct ste_softc *sc)
{
int i;
for (i = 0; i < STE_TIMEOUT; i++) {
if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG))
break;
}
if (i == STE_TIMEOUT)
printf("%s: command never completed!\n", sc->sc_dev.dv_xname);
}
