static void dump_mb(struct cx18 *cx, struct cx18_mailbox *mb, char *name)
{
char argstr[MAX_MB_ARGUMENTS*11+1];
if (!(cx18_debug & CX18_DBGFLG_API))
return;
CX18_DEBUG_API("%s: req %#010x ack %#010x cmd %#010x err %#010x args%s"
"\n", name, mb->request, mb->ack, mb->cmd, mb->error,
u32arr2hex(mb->args, MAX_MB_ARGUMENTS, argstr));
}
static int cx18_api_call(struct cx18 *cx, u32 cmd, int args, u32 data[])
{
const struct cx18_api_info *info = find_api_info(cmd);
u32 state, irq, req, ack, err;
struct cx18_mailbox __iomem *mb;
u32 __iomem *xpu_state;
wait_queue_head_t *waitq;
struct mutex *mb_lock;
long int timeout, ret;
int i;
char argstr[MAX_MB_ARGUMENTS*11+1];
if (info == NULL) {
CX18_WARN("unknown cmd %x\n", cmd);
return -EINVAL;
}
if (cx18_debug & CX18_DBGFLG_API) { /* only call u32arr2hex if needed */
if (cmd == CX18_CPU_DE_SET_MDL) {
if (cx18_debug & CX18_DBGFLG_HIGHVOL)
CX18_DEBUG_HI_API("%s\tcmd %#010x args%s\n",
info->name, cmd,
u32arr2hex(data, args, argstr));
} else
CX18_DEBUG_API("%s\tcmd %#010x args%s\n",
info->name, cmd,
u32arr2hex(data, args, argstr));
}
switch (info->rpu) {
case APU:
waitq = &cx->mb_apu_waitq;
mb_lock = &cx->epu2apu_mb_lock;
irq = IRQ_EPU_TO_APU;
mb = &cx->scb->epu2apu_mb;
xpu_state = &cx->scb->apu_state;
break;
case CPU:
waitq = &cx->mb_cpu_waitq;
mb_lock = &cx->epu2cpu_mb_lock;
irq = IRQ_EPU_TO_CPU;
mb = &cx->scb->epu2cpu_mb;
xpu_state = &cx->scb->cpu_state;
break;
default:
CX18_WARN("Unknown RPU (%d) for API call\n", info->rpu);
return -EINVAL;
}
mutex_lock(mb_lock);
/*
* Wait for an in-use mailbox to complete
*
* If the XPU is responding with Ack's, the mailbox shouldn't be in
* a busy state, since we serialize access to it on our end.
*
* If the wait for ack after sending a previous command was interrupted
* by a signal, we may get here and find a busy mailbox. After waiting,
* mark it "not busy" from our end, if the XPU hasn't ack'ed it still.
*/
state = cx18_readl(cx, xpu_state);
req = cx18_readl(cx, &mb->request);
timeout = msecs_to_jiffies(10);
ret = wait_event_timeout(*waitq,
(ack = cx18_readl(cx, &mb->ack)) == req,
timeout);
if (req != ack) {
/* waited long enough, make the mbox "not busy" from our end */
cx18_writel(cx, req, &mb->ack);
CX18_ERR("mbox was found stuck busy when setting up for %s; "
"clearing busy and trying to proceed\n", info->name);
} else if (ret != timeout)
CX18_DEBUG_API("waited %u msecs for busy mbox to be acked\n",
jiffies_to_msecs(timeout-ret));
/* Build the outgoing mailbox */
req = ((req & 0xfffffffe) == 0xfffffffe) ? 1 : req + 1;
cx18_writel(cx, cmd, &mb->cmd);
for (i = 0; i < args; i++)
cx18_writel(cx, data[i], &mb->args[i]);
cx18_writel(cx, 0, &mb->error);
cx18_writel(cx, req, &mb->request);
cx18_writel(cx, req - 1, &mb->ack); /* ensure ack & req are distinct */
/*
* Notify the XPU and wait for it to send an Ack back
*/
timeout = msecs_to_jiffies((info->flags & API_FAST) ? 10 : 20);
CX18_DEBUG_HI_IRQ("sending interrupt SW1: %x to send %s\n",
irq, info->name);
cx18_write_reg_expect(cx, irq, SW1_INT_SET, irq, irq);
ret = wait_event_timeout(
*waitq,
cx18_readl(cx, &mb->ack) == cx18_readl(cx, &mb->request),
timeout);
if (ret == 0) {
/* Timed out */
mutex_unlock(mb_lock);
CX18_DEBUG_WARN("sending %s timed out waiting %d msecs for RPU "
"acknowledgement\n",
info->name, jiffies_to_msecs(timeout));
return -EINVAL;
}
if (ret != timeout)
CX18_DEBUG_HI_API("waited %u msecs for %s to be acked\n",
jiffies_to_msecs(timeout-ret), info->name);
/* Collect data returned by the XPU */
for (i = 0; i < MAX_MB_ARGUMENTS; i++)
data[i] = cx18_readl(cx, &mb->args[i]);
err = cx18_readl(cx, &mb->error);
mutex_unlock(mb_lock);
/*
* Wait for XPU to perform extra actions for the caller in some cases.
* e.g. CX18_CPU_DE_RELEASE_MDL will cause the CPU to send all buffers
* back in a burst shortly thereafter
*/
if (info->flags & API_SLOW)
cx18_msleep_timeout(300, 0);
if (err)
CX18_DEBUG_API("mailbox error %08x for command %s\n", err,
info->name);
return err ? -EIO : 0;
}
static int cx18_api_call(struct cx18 *cx, u32 cmd, int args, u32 data[])
{
const struct cx18_api_info *info = find_api_info(cmd);
u32 state = 0, irq = 0, req, oldreq, err;
struct cx18_mailbox __iomem *mb;
wait_queue_head_t *waitq;
int timeout = 100;
int cnt = 0;
int sig = 0;
int i;
if (info == NULL) {
CX18_WARN("unknown cmd %x\n", cmd);
return -EINVAL;
}
if (cmd == CX18_CPU_DE_SET_MDL)
CX18_DEBUG_HI_API("%s\n", info->name);
else
CX18_DEBUG_API("%s\n", info->name);
cx18_setup_page(cx, SCB_OFFSET);
mb = cx18_mb_is_complete(cx, info->rpu, &state, &irq, &req);
if (mb == NULL) {
CX18_ERR("mb %s busy\n", info->name);
return -EBUSY;
}
oldreq = req - 1;
cx18_writel(cx, cmd, &mb->cmd);
for (i = 0; i < args; i++)
cx18_writel(cx, data[i], &mb->args[i]);
cx18_writel(cx, 0, &mb->error);
cx18_writel(cx, req, &mb->request);
switch (info->rpu) {
case APU: waitq = &cx->mb_apu_waitq; break;
case CPU: waitq = &cx->mb_cpu_waitq; break;
case EPU: waitq = &cx->mb_epu_waitq; break;
case HPU: waitq = &cx->mb_hpu_waitq; break;
default: return -EINVAL;
}
if (info->flags & API_FAST)
timeout /= 2;
cx18_write_reg(cx, irq, SW1_INT_SET);
while (!sig && cx18_readl(cx, &mb->ack) != cx18_readl(cx, &mb->request)
&& cnt < 660) {
if (cnt > 200 && !in_atomic())
sig = cx18_msleep_timeout(10, 1);
cnt++;
}
if (sig)
return -EINTR;
if (cnt == 660) {
cx18_writel(cx, oldreq, &mb->request);
CX18_ERR("mb %s failed\n", info->name);
return -EINVAL;
}
for (i = 0; i < MAX_MB_ARGUMENTS; i++)
data[i] = cx18_readl(cx, &mb->args[i]);
err = cx18_readl(cx, &mb->error);
if (!in_atomic() && (info->flags & API_SLOW))
cx18_msleep_timeout(300, 0);
if (err)
CX18_DEBUG_API("mailbox error %08x for command %s\n", err,
info->name);
return err ? -EIO : 0;
}