void
cyg_hal_plf_scif_init_channel(channel_data_t* chan)
{
cyg_uint8* base = chan->base;
cyg_uint8 tmp;
cyg_uint16 sr;
int baud_rate = CYGNUM_HAL_SH_SH2_SCIF_BAUD_RATE;
// Disable everything.
HAL_WRITE_UINT8(base+_REG_SCSCR, 0);
// Reset FIFO.
HAL_WRITE_UINT8(base+_REG_SCFCR,
CYGARC_REG_SCIF_SCFCR_TFRST|CYGARC_REG_SCIF_SCFCR_RFRST);
HAL_WRITE_UINT16(base+_REG_SCFER, 0);
// 8-1-no parity. This is also fine for IrDA mode
HAL_WRITE_UINT8(base+_REG_SCSMR, 0);
if (chan->irda_mode)
HAL_WRITE_UINT8(base+_REG_SCIMR, CYGARC_REG_SCIF_SCIMR_IRMOD);
else {
HAL_WRITE_UINT8(base+_REG_SCIMR, 0);
}
// Set speed to CYGNUM_HAL_SH_SH2_SCIF_DEFAULT_BAUD_RATE
HAL_READ_UINT8(base+_REG_SCSMR, tmp);
tmp &= ~CYGARC_REG_SCIF_SCSMR_CKSx_MASK;
tmp |= CYGARC_SCBRR_CKSx(baud_rate);
HAL_WRITE_UINT8(base+_REG_SCSMR, tmp);
HAL_WRITE_UINT8(base+_REG_SCBRR, CYGARC_SCBRR_N(baud_rate));
// Let things settle: Here we should should wait the equivalent of
// one bit interval,
// i.e. 1/CYGNUM_HAL_SH_SH2_SCIF_DEFAULT_BAUD_RATE second, but
// until we have something like the Linux delay loop, it's hard to
// do reliably. So just move on and hope for the best (this is
// unlikely to cause problems since the CPU has just come out of
// reset anyway).
// Clear status register (read back first).
HAL_READ_UINT16(base+_REG_SCSSR, sr);
HAL_WRITE_UINT16(base+_REG_SCSSR, 0);
HAL_WRITE_UINT8(base+_REG_SC2SSR, CYGARC_REG_SCIF_SC2SSR_BITRATE_16|CYGARC_REG_SCIF_SC2SSR_EI);
// Bring FIFO out of reset and set to trigger on every char in
// FIFO (or C-c input would not be processed).
HAL_WRITE_UINT8(base+_REG_SCFCR,
CYGARC_REG_SCIF_SCFCR_RTRG_1|CYGARC_REG_SCIF_SCFCR_TTRG_1);
// Leave Tx/Rx interrupts disabled, but enable Rx/Tx (only Rx for IrDA)
if (chan->irda_mode)
HAL_WRITE_UINT8(base+_REG_SCSCR, CYGARC_REG_SCIF_SCSCR_RE);
#ifdef CYGHWR_HAL_SH_SH2_SCIF_ASYNC_RXTX
else if (chan->async_rxtx_mode)
HAL_WRITE_UINT8(base+_REG_SCSCR, CYGARC_REG_SCIF_SCSCR_RE);
#endif
else
HAL_WRITE_UINT8(base+_REG_SCSCR, CYGARC_REG_SCIF_SCSCR_TE|CYGARC_REG_SCIF_SCSCR_RE);
}
void
cyg_hal_plf_scif_init_channel(channel_data_t* chan)
{
cyg_uint8* base = chan->base;
cyg_uint8 tmp;
cyg_uint16 sr;
// Disable everything.
HAL_WRITE_UINT8(base+_REG_SCSCR, 0);
// Reset FIFO.
HAL_WRITE_UINT8(base+_REG_SCFCR,
CYGARC_REG_SCIF_SCFCR_TFRST|CYGARC_REG_SCIF_SCFCR_RFRST);
// 8-1-no parity.
HAL_WRITE_UINT8(base+_REG_SCSMR, 0);
// Set speed to CYGNUM_HAL_SH_SH3_SCIF_DEFAULT_BAUD_RATE
HAL_READ_UINT8(base+_REG_SCSMR, tmp);
tmp &= ~CYGARC_REG_SCIF_SCSMR_CKSx_MASK;
tmp |= CYGARC_SCBRR_CKSx(CYGNUM_HAL_SH_SH3_SCIF_BAUD_RATE);
HAL_WRITE_UINT8(base+_REG_SCSMR, tmp);
HAL_WRITE_UINT8(base+_REG_SCBRR, CYGARC_SCBRR_N(CYGNUM_HAL_SH_SH3_SCIF_BAUD_RATE));
// Let things settle: Here we should should wait the equivalent of
// one bit interval,
// i.e. 1/CYGNUM_HAL_SH_SH3_SCIF_DEFAULT_BAUD_RATE second, but
// until we have something like the Linux delay loop, it's hard to
// do reliably. So just move on and hope for the best (this is
// unlikely to cause problems since the CPU has just come out of
// reset anyway).
// Clear status register (read back first).
HAL_READ_UINT16(base+_REG_SCSSR, sr);
HAL_WRITE_UINT16(base+_REG_SCSSR, 0);
// Bring FIFO out of reset and set to trigger on every char in
// FIFO (or C-c input would not be processed).
HAL_WRITE_UINT8(base+_REG_SCFCR,
CYGARC_REG_SCIF_SCFCR_RTRG_1|CYGARC_REG_SCIF_SCFCR_TTRG_1);
// Leave Tx/Rx interrupts disabled, but enable Tx/Rx
HAL_WRITE_UINT8(base+_REG_SCSCR,
CYGARC_REG_SCIF_SCSCR_TE|CYGARC_REG_SCIF_SCSCR_RE);
}
static void
cyg_hal_plf_scif_set_baud(cyg_uint8 *base, cyg_uint32 baud)
{
cyg_uint16 tmp;
// Set desired baudrate
HAL_READ_UINT16(base+_REG_SCSMR, tmp);
tmp &= ~CYGARC_REG_SCIF_SCSMR_CKSx_MASK;
tmp |= CYGARC_SCBRR_CKSx(baud);
HAL_WRITE_UINT16(base+_REG_SCSMR, tmp);
HAL_WRITE_UINT8(base+_REG_SCBRR,
CYGARC_SCBRR_N(baud));
// Let things settle: Here we should wait the equivalent of
// one bit interval, i.e. 1/<baudrate> second, but we'll wait twice
// that to be sure.
CYGACC_CALL_IF_DELAY_US(2000000/baud);
}
void
cyg_hal_plf_sci_init_channel(channel_data_t* chan)
{
cyg_uint8 tmp;
cyg_uint8* base = chan->base;
// Disable Tx/Rx interrupts, but enable Tx/Rx
HAL_WRITE_UINT8(base+_REG_SCSCR,
CYGARC_REG_SCI_SCSCR_TE|CYGARC_REG_SCI_SCSCR_RE);
// 8-1-no parity.
HAL_WRITE_UINT8(base+_REG_SCSMR, 0);
// Set speed to CYGNUM_HAL_SH_SH2_SCI_DEFAULT_BAUD_RATE
HAL_READ_UINT8(base+_REG_SCSMR, tmp);
tmp &= ~CYGARC_REG_SCI_SCSMR_CKSx_MASK;
tmp |= CYGARC_SCBRR_CKSx(CYGNUM_HAL_SH_SH2_SCI_BAUD_RATE);
HAL_WRITE_UINT8(base+_REG_SCSMR, tmp);
HAL_WRITE_UINT8(base+_REG_SCBRR, CYGARC_SCBRR_N(CYGNUM_HAL_SH_SH2_SCI_BAUD_RATE));
}
0, // 1 stop bit
-1,
CYGARC_REG_SCIF_SCSMR_STOP // 2 stop bits
};
static short select_parity[] = {
0, // No parity
CYGARC_REG_SCIF_SCSMR_PE, // Even parity
CYGARC_REG_SCIF_SCSMR_PE|CYGARC_REG_SCIF_SCSMR_OE, // Odd parity
-1,
-1
};
static unsigned short select_baud[] = {
0, // Unused
CYGARC_SCBRR_CKSx(50)<<8 | CYGARC_SCBRR_N(50),
CYGARC_SCBRR_CKSx(75)<<8 | CYGARC_SCBRR_N(75),
CYGARC_SCBRR_CKSx(110)<<8 | CYGARC_SCBRR_N(110),
CYGARC_SCBRR_CKSx(134)<<8 | CYGARC_SCBRR_N(134),
CYGARC_SCBRR_CKSx(150)<<8 | CYGARC_SCBRR_N(150),
CYGARC_SCBRR_CKSx(200)<<8 | CYGARC_SCBRR_N(200),
CYGARC_SCBRR_CKSx(300)<<8 | CYGARC_SCBRR_N(300),
CYGARC_SCBRR_CKSx(600)<<8 | CYGARC_SCBRR_N(600),
CYGARC_SCBRR_CKSx(1200)<<8 | CYGARC_SCBRR_N(1200),
CYGARC_SCBRR_CKSx(1800)<<8 | CYGARC_SCBRR_N(1800),
CYGARC_SCBRR_CKSx(2400)<<8 | CYGARC_SCBRR_N(2400),
CYGARC_SCBRR_CKSx(3600)<<8 | CYGARC_SCBRR_N(3600),
CYGARC_SCBRR_CKSx(4800)<<8 | CYGARC_SCBRR_N(4800),
CYGARC_SCBRR_CKSx(7200)<<8 | CYGARC_SCBRR_N(7200),
CYGARC_SCBRR_CKSx(9600)<<8 | CYGARC_SCBRR_N(9600),
CYGARC_SCBRR_CKSx(14400)<<8 | CYGARC_SCBRR_N(14400),
